msm: camera: tfe: Remove hardcoding of shift values

Problem Description:
Hardcoded shift values may vary with targets.

Solution:
Add support for reading shift values from target specific
header file to avoid hardcoding in tfe_bus and tfe_core files .

CRs-Fixed: 3390902
Change-Id: I7960e72f6b15c13c07cacc28a83fc27e7f452d8d
Signed-off-by: Stuti Saxena <[email protected]>

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe530.h

@@ -69,6 +69,8 @@ static struct cam_tfe_top_reg_offset_common  tfe530_top_commong_reg  = {
 	.rdi2_overflow_bit                      = BIT(19),
 	.mup_shift_val                          = 0,
 	.mup_supported                          = false,
+	.height_shift                           = 16,
+	.epoch_shift_val                        = 16,
 };
 
 static struct cam_tfe_camif_reg  tfe530_camif_reg = {
@@ -874,6 +876,8 @@ static struct cam_tfe_bus_hw_info  tfe530_bus_hw_info = {
 	.max_bw_counter_limit  = 0xFF,
 	.counter_limit_shift   = 1,
 	.counter_limit_mask    = 0xF,
+	.en_cfg_shift = 16,
+	.height_shift = 16,
 };
 
 struct cam_tfe_hw_info cam_tfe530 = {

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe640.h

@@ -82,6 +82,8 @@ static struct cam_tfe_top_reg_offset_common  tfe640_top_commong_reg  = {
 	.rdi2_overflow_bit                      = BIT(19),
 	.mup_shift_val                          = 0,
 	.mup_supported                          = false,
+	.height_shift                           = 16,
+	.epoch_shift_val                        = 16,
 };
 
 static struct cam_tfe_camif_reg  tfe640_camif_reg = {
@@ -1190,6 +1192,8 @@ static struct cam_tfe_bus_hw_info  tfe640_bus_hw_info = {
 	.max_bw_counter_limit  = 0xFF,
 	.counter_limit_shift   = 1,
 	.counter_limit_mask    = 0xF,
+	.en_cfg_shift = 16,
+	.height_shift = 16,
 };
 
 struct cam_tfe_hw_info cam_tfe640 = {

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.c

@@ -71,6 +71,8 @@ struct cam_tfe_bus_common_data {
 	uint32_t                                    num_sec_out;
 	uint32_t                                    comp_done_shift;
 	uint32_t                                    rdi_width;
+	uint32_t                                    en_cfg_shift;
+	uint32_t                                    height_shift;
 	bool                                        is_lite;
 	bool                                        support_consumed_addr;
 	cam_hw_mgr_event_cb_func                    event_cb;
@@ -602,7 +604,7 @@ static int cam_tfe_bus_acquire_rdi_wm(
 {
 	int pack_fmt = 0;
 	int rdi_width = rsrc_data->common_data->rdi_width;
-
+	int en_cfg_shift = rsrc_data->common_data->en_cfg_shift;
 	if (rdi_width == 64)
 		pack_fmt = 0xa;
 	else if (rdi_width == 128)
@@ -622,7 +624,7 @@ static int cam_tfe_bus_acquire_rdi_wm(
 			rsrc_data->height = 0;
 			rsrc_data->stride =
 				CAM_TFE_RDI_BUS_DEFAULT_STRIDE;
-			rsrc_data->en_cfg = (0x1 << 16) | 0x1;
+			rsrc_data->en_cfg = (0x1 << en_cfg_shift) | 0x1;
 		}
 		break;
 	case CAM_FORMAT_MIPI_RAW_8:
@@ -639,7 +641,7 @@ static int cam_tfe_bus_acquire_rdi_wm(
 			rsrc_data->height = 0;
 			rsrc_data->stride =
 				CAM_TFE_RDI_BUS_DEFAULT_STRIDE;
-			rsrc_data->en_cfg = (0x1 << 16) | 0x1;
+			rsrc_data->en_cfg = (0x1 << en_cfg_shift) | 0x1;
 		}
 		break;
 	case CAM_FORMAT_MIPI_RAW_10:
@@ -655,7 +657,7 @@ static int cam_tfe_bus_acquire_rdi_wm(
 			rsrc_data->height = 0;
 			rsrc_data->stride =
 				CAM_TFE_RDI_BUS_DEFAULT_STRIDE;
-			rsrc_data->en_cfg = (0x1 << 16) | 0x1;
+			rsrc_data->en_cfg = (0x1 << en_cfg_shift) | 0x1;
 		}
 		break;
 	case CAM_FORMAT_MIPI_RAW_12:
@@ -671,7 +673,7 @@ static int cam_tfe_bus_acquire_rdi_wm(
 			rsrc_data->height = 0;
 			rsrc_data->stride =
 				CAM_TFE_RDI_BUS_DEFAULT_STRIDE;
-			rsrc_data->en_cfg = (0x1 << 16) | 0x1;
+			rsrc_data->en_cfg = (0x1 << en_cfg_shift) | 0x1;
 		}
 		break;
 	case CAM_FORMAT_MIPI_RAW_14:
@@ -687,7 +689,7 @@ static int cam_tfe_bus_acquire_rdi_wm(
 			rsrc_data->height = 0;
 			rsrc_data->stride =
 				CAM_TFE_RDI_BUS_DEFAULT_STRIDE;
-			rsrc_data->en_cfg = (0x1 << 16) | 0x1;
+			rsrc_data->en_cfg = (0x1 << en_cfg_shift) | 0x1;
 		}
 		break;
 	case CAM_FORMAT_PLAIN16_10:
@@ -707,7 +709,7 @@ static int cam_tfe_bus_acquire_rdi_wm(
 			rsrc_data->height = 0;
 			rsrc_data->stride =
 				CAM_TFE_RDI_BUS_DEFAULT_STRIDE;
-			rsrc_data->en_cfg = (0x1 << 16) | 0x1;
+			rsrc_data->en_cfg = (0x1 << en_cfg_shift) | 0x1;
 		}
 		break;
 
@@ -725,7 +727,7 @@ static int cam_tfe_bus_acquire_rdi_wm(
 			rsrc_data->height = 0;
 			rsrc_data->stride =
 				CAM_TFE_RDI_BUS_DEFAULT_STRIDE;
-			rsrc_data->en_cfg = (0x1 << 16) | 0x1;
+			rsrc_data->en_cfg = (0x1 << en_cfg_shift) | 0x1;
 		}
 		break;
 	default:
@@ -752,7 +754,6 @@ static int cam_tfe_bus_acquire_wm(
 	struct cam_tfe_bus_wm_resource_data  *rsrc_data = NULL;
 	uint32_t wm_idx = 0;
 	int rc = 0;
-
 	*wm_res = NULL;
 	/* No need to allocate for BUS TFE OUT to WM is fixed. */
 	if (bus_priv->common_data.is_lite)
@@ -862,7 +863,7 @@ static int cam_tfe_bus_acquire_wm(
 		rsrc_data->width = 0;
 		rsrc_data->height = 0;
 		rsrc_data->stride = 1;
-		rsrc_data->en_cfg = (0x1 << 16) | 0x1;
+		rsrc_data->en_cfg = (0x1 << rsrc_data->common_data->en_cfg_shift) | 0x1;
 
 		/*RS state packet format*/
 		if (rsrc_data->index == 15)
@@ -919,13 +920,15 @@ static int cam_tfe_bus_start_wm(struct cam_isp_resource_node *wm_res)
 		wm_res->res_priv;
 	struct cam_tfe_bus_common_data        *common_data =
 		rsrc_data->common_data;
+	int height_shift = rsrc_data->common_data->height_shift;
 
 	/* Skip to overwrite if wm bandwidth limiter blob already sent */
 	if (!rsrc_data->limiter_blob_status)
 		cam_io_w(rsrc_data->common_data->counter_limit_mask,
 			common_data->mem_base + rsrc_data->hw_regs->bw_limit);
 
-	cam_io_w((rsrc_data->height << 16) | rsrc_data->width,
+	cam_io_w(0xf, common_data->mem_base + rsrc_data->hw_regs->bw_limit);
+	cam_io_w((rsrc_data->height << height_shift) | rsrc_data->width,
 		common_data->mem_base + rsrc_data->hw_regs->image_cfg_0);
 	cam_io_w(rsrc_data->pack_fmt,
 		common_data->mem_base + rsrc_data->hw_regs->packer_cfg);
@@ -2118,7 +2121,8 @@ static int cam_tfe_bus_update_wm(void *priv, void *cmd_args,
 
 		wm_data = tfe_out_data->wm_res[i]->res_priv;
 		/* update width register */
-		val = ((wm_data->height << 16) | (wm_data->width & 0xFFFF));
+		val = ((wm_data->height << wm_data->common_data->height_shift) |
+			(wm_data->width & 0xFFFF));
 		CAM_TFE_ADD_REG_VAL_PAIR(reg_val_pair, j,
 			wm_data->hw_regs->image_cfg_0, val);
 		CAM_DBG(CAM_ISP, "WM:%d image height and width 0x%x",
@@ -2728,6 +2732,8 @@ int cam_tfe_bus_init(
 	bus_priv->common_data.max_bw_counter_limit = hw_info->max_bw_counter_limit;
 	bus_priv->common_data.counter_limit_shift = hw_info->counter_limit_shift;
 	bus_priv->common_data.counter_limit_mask = hw_info->counter_limit_mask;
+	bus_priv->common_data.en_cfg_shift = hw_info->en_cfg_shift;
+	bus_priv->common_data.height_shift = hw_info->height_shift;
 
 	for (i = 0; i < CAM_TFE_BUS_IRQ_REGISTERS_MAX; i++)
 		bus_priv->bus_irq_error_mask[i] =

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_bus.h

@@ -201,6 +201,7 @@ struct cam_tfe_bus_tfe_out_hw_info {
  * @max_bw_counter_limit:  Max BW counter limit
  * @counter_limit_shift:   Mask shift for BW counter limit
  * @counter_limit_mask:    Default Mask of BW limit counter
+ * @en_cfg_shift:          bus client frame based enable bit
  */
 struct cam_tfe_bus_hw_info {
 	struct cam_tfe_bus_reg_offset_common common_reg;
@@ -213,6 +214,8 @@ struct cam_tfe_bus_hw_info {
 	uint32_t num_comp_grp;
 	uint32_t max_wm_per_comp_grp;
 	uint32_t comp_done_shift;
+	uint32_t en_cfg_shift;
+	uint32_t height_shift;
 	uint32_t top_bus_wr_irq_shift;
 	uint32_t comp_buf_done_mask;
 	uint32_t comp_rup_done_mask;

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c

@@ -239,9 +239,11 @@ static void cam_tfe_log_tfe_in_debug_status(
 	void __iomem                         *mem_base;
 	struct cam_tfe_camif_data            *camif_data;
 	struct cam_tfe_rdi_data              *rdi_data;
+	struct cam_tfe_top_reg_offset_common *common_reg;
 	uint32_t  i, val_0, val_1;
 
 	mem_base = top_priv->common_data.soc_info->reg_map[0].mem_base;
+	common_reg = top_priv->common_data.common_reg;
 
 	for (i = 0; i < CAM_TFE_TOP_IN_PORT_MAX; i++) {
 		if ((top_priv->in_rsrc[i].res_state !=
@@ -258,7 +260,7 @@ static void cam_tfe_log_tfe_in_debug_status(
 			CAM_INFO(CAM_ISP,
 				"camif debug1:0x%x Height:0x%x, width:0x%x",
 				val_1,
-				((val_0 >> 16) & 0x1FFF),
+				((val_0 >> common_reg->height_shift) & 0x1FFF),
 				(val_0 & 0x1FFF));
 			CAM_INFO(CAM_ISP,
 				"Acquired sync mode:%d left start pxl:0x%x end_pixel:0x%x",
@@ -294,7 +296,7 @@ static void cam_tfe_log_tfe_in_debug_status(
 			CAM_INFO(CAM_ISP,
 				"RDI res id:%d debug1:0x%x Height:0x%x, width:0x%x",
 				top_priv->in_rsrc[i].res_id,
-				val_1, ((val_0 >> 16) & 0x1FFF),
+				val_1, ((val_0 >> common_reg->height_shift) & 0x1FFF),
 				(val_0 & 0x1FFF));
 			CAM_INFO(CAM_ISP,
 				"sync mode:%d left start pxl:0x%x end_pixel:0x%x",
@@ -415,7 +417,8 @@ static void cam_tfe_log_error_irq_status(
 			CAM_INFO(CAM_ISP,
 				"TFE %d SENSOR_SWITCH_OUT_OF_SYNC_FRAME_DROP mup: last %d curr %d",
 				core_info->core_index, top_priv->last_mup_val,
-				((cam_io_r(mem_base + common_reg->reg_update_cmd) >> 8) & 1));
+				((cam_io_r(mem_base + common_reg->reg_update_cmd) >>
+				common_reg->mup_shift_val) & 1));
 		}
 	}
 
@@ -2060,6 +2063,7 @@ static int cam_tfe_camif_resource_start(
 	uint32_t                             camera_hw_version = 0;
 	struct cam_hw_intf                  *tfe_device;
 	bool                                 pdaf_rdi2_mux_en = false;
+	struct cam_tfe_top_reg_offset_common *common_reg;
 
 	if (!camif_res || !core_info) {
 		CAM_ERR(CAM_ISP, "Error Invalid input arguments");
@@ -2081,7 +2085,7 @@ static int cam_tfe_camif_resource_start(
 			core_info->core_index);
 		return -ENODEV;
 	}
-
+	common_reg = top_priv->common_data.common_reg;
 	/* Config tfe core*/
 	val = 0;
 	if (rsrc_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE)
@@ -2150,7 +2154,7 @@ static int cam_tfe_camif_resource_start(
 
 	epoch1_irq_mask = rsrc_data->reg_data->epoch_line_cfg &
 			0xFFFF;
-	computed_epoch_line_cfg = (epoch0_irq_mask << 16) |
+	computed_epoch_line_cfg = (epoch0_irq_mask << common_reg->epoch_shift_val) |
 			epoch1_irq_mask;
 	cam_io_w_mb(computed_epoch_line_cfg,
 			rsrc_data->mem_base +

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.h

@@ -130,6 +130,8 @@ struct cam_tfe_top_reg_offset_common {
 	uint32_t rdi1_overflow_bit;
 	uint32_t rdi2_overflow_bit;
 	uint32_t out_of_sync_frame_drop_bit;
+	uint32_t height_shift;
+	uint32_t epoch_shift_val;
 
 	/* configuration */
 	bool serializer_supported;