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+/* SPDX-License-Identifier: GPL-2.0-only */
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+/*
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+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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+ */
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+
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+#ifndef _CAM_TFE_CSID_770_H_
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+#define _CAM_TFE_CSID_770_H_
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+
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+#include "cam_tfe_csid_core.h"
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+
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+#define CAM_TFE_CSID_VERSION_V770 0x70070000
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+
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+static struct cam_tfe_csid_pxl_reg_offset cam_tfe_csid_770_ipp_reg_offset = {
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+ .csid_pxl_irq_status_addr = 0x30,
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+ .csid_pxl_irq_mask_addr = 0x34,
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+ .csid_pxl_irq_clear_addr = 0x38,
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+ .csid_pxl_irq_set_addr = 0x3c,
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+
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+ .csid_pxl_cfg0_addr = 0x200,
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+ .csid_pxl_cfg1_addr = 0x204,
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+ .csid_pxl_ctrl_addr = 0x208,
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+ .csid_pxl_frame_drop_pattern = 0x20c,
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+ .csid_pxl_frame_drop_period = 0x210,
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+ .csid_pxl_irq_subsample_pattern = 0x214,
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+ .csid_pxl_irq_subsample_period = 0x218,
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+ .csid_pxl_hcrop_addr = 0x21c,
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+ .csid_pxl_vcrop_addr = 0x220,
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+ .csid_pxl_rst_strobes_addr = 0x240,
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+ .csid_pxl_status_addr = 0x254,
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+ .csid_pxl_misr_val_addr = 0x258,
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+ .csid_pxl_format_measure_cfg0_addr = 0x270,
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+ .csid_pxl_format_measure_cfg1_addr = 0x274,
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+ .csid_pxl_format_measure0_addr = 0x278,
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+ .csid_pxl_format_measure1_addr = 0x27c,
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+ .csid_pxl_format_measure2_addr = 0x280,
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+ .csid_pxl_timestamp_curr0_sof_addr = 0x290,
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+ .csid_pxl_timestamp_curr1_sof_addr = 0x294,
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+ .csid_pxl_timestamp_perv0_sof_addr = 0x298,
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+ .csid_pxl_timestamp_perv1_sof_addr = 0x29c,
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+ .csid_pxl_timestamp_curr0_eof_addr = 0x2a0,
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+ .csid_pxl_timestamp_curr1_eof_addr = 0x2a4,
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+ .csid_pxl_timestamp_perv0_eof_addr = 0x2a8,
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+ .csid_pxl_timestamp_perv1_eof_addr = 0x2ac,
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+ .csid_pxl_err_recovery_cfg0_addr = 0x2d0,
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+ .csid_pxl_err_recovery_cfg1_addr = 0x2d4,
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+ .csid_pxl_err_recovery_cfg2_addr = 0x2d8,
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+ .csid_pxl_multi_vcdt_cfg0_addr = 0x2dc,
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+
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+ /* configurations */
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+ .pix_store_en_shift_val = 7,
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+ .early_eof_en_shift_val = 29,
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+ .halt_master_sel_shift = 4,
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+ .halt_mode_shift = 2,
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+ .halt_master_sel_master_val = 3,
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+ .halt_master_sel_slave_val = 0,
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+ .binning_supported = 3,
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+ .bin_qcfa_en_shift_val = 30,
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+ .bin_en_shift_val = 2,
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+ .is_multi_vc_dt_supported = true,
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+ .format_measure_en_shift_val = 0,
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+ .measure_en_hbi_vbi_cnt_val = 0xc,
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+};
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+
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+static struct cam_tfe_csid_pxl_reg_offset cam_tfe_csid_770_ppp_reg_offset = {
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+ .csid_pxl_irq_status_addr = 0xA0,
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+ .csid_pxl_irq_mask_addr = 0xA4,
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+ .csid_pxl_irq_clear_addr = 0xA8,
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+ .csid_pxl_irq_set_addr = 0xAc,
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+
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+ .csid_pxl_cfg0_addr = 0x700,
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+ .csid_pxl_cfg1_addr = 0x704,
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+ .csid_pxl_ctrl_addr = 0x708,
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+ .csid_pxl_frame_drop_pattern = 0x70c,
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+ .csid_pxl_frame_drop_period = 0x710,
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+ .csid_pxl_irq_subsample_pattern = 0x714,
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+ .csid_pxl_irq_subsample_period = 0x718,
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+ .csid_pxl_hcrop_addr = 0x71c,
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+ .csid_pxl_vcrop_addr = 0x720,
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+ .csid_pxl_rst_strobes_addr = 0x740,
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+ .csid_pxl_status_addr = 0x754,
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+ .csid_pxl_misr_val_addr = 0x758,
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+ .csid_pxl_format_measure_cfg0_addr = 0x770,
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+ .csid_pxl_format_measure_cfg1_addr = 0x774,
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+ .csid_pxl_format_measure0_addr = 0x778,
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+ .csid_pxl_format_measure1_addr = 0x77c,
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+ .csid_pxl_format_measure2_addr = 0x780,
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+ .csid_pxl_timestamp_curr0_sof_addr = 0x790,
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+ .csid_pxl_timestamp_curr1_sof_addr = 0x794,
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+ .csid_pxl_timestamp_perv0_sof_addr = 0x798,
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+ .csid_pxl_timestamp_perv1_sof_addr = 0x79c,
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+ .csid_pxl_timestamp_curr0_eof_addr = 0x7a0,
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+ .csid_pxl_timestamp_curr1_eof_addr = 0x7a4,
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+ .csid_pxl_timestamp_perv0_eof_addr = 0x7a8,
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+ .csid_pxl_timestamp_perv1_eof_addr = 0x7ac,
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+ .csid_pxl_ppp_sparse_pd_ext_cfg0 = 0x7c0,
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+ .csid_pxl_err_recovery_cfg0_addr = 0x7d0,
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+ .csid_pxl_err_recovery_cfg1_addr = 0x7d4,
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+ .csid_pxl_err_recovery_cfg2_addr = 0x7d8,
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+ .csid_pxl_multi_vcdt_cfg0_addr = 0x7dc,
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+
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+ /* configurations */
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+ .pix_store_en_shift_val = 7,
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+ .early_eof_en_shift_val = 29,
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+ .halt_master_sel_shift = 4,
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+ .halt_mode_shift = 2,
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+ .halt_master_sel_master_val = 3,
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+ .halt_master_sel_slave_val = 0,
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+ .binning_supported = 0,
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+ .bin_qcfa_en_shift_val = 30,
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+ .bin_en_shift_val = 2,
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+ .is_multi_vc_dt_supported = true,
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+ .format_measure_en_shift_val = 0,
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+ .measure_en_hbi_vbi_cnt_val = 0xc,
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+};
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+
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+static struct cam_tfe_csid_rdi_reg_offset cam_tfe_csid_770_rdi_0_reg_offset = {
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+ .csid_rdi_irq_status_addr = 0x40,
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+ .csid_rdi_irq_mask_addr = 0x44,
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+ .csid_rdi_irq_clear_addr = 0x48,
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+ .csid_rdi_irq_set_addr = 0x4c,
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+
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+ .csid_rdi_cfg0_addr = 0x300,
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+ .csid_rdi_cfg1_addr = 0x304,
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+ .csid_rdi_ctrl_addr = 0x308,
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+ .csid_rdi_frame_drop_pattern = 0x30c,
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+ .csid_rdi_frame_drop_period = 0x310,
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+ .csid_rdi_irq_subsample_pattern = 0x314,
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+ .csid_rdi_irq_subsample_period = 0x318,
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+ .csid_rdi_rst_strobes_addr = 0x340,
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+ .csid_rdi_status_addr = 0x350,
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+ .csid_rdi_misr_val0_addr = 0x354,
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+ .csid_rdi_misr_val1_addr = 0x358,
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+ .csid_rdi_misr_val2_addr = 0x35c,
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+ .csid_rdi_misr_val3_addr = 0x360,
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+ .csid_rdi_format_measure_cfg0_addr = 0x370,
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+ .csid_rdi_format_measure_cfg1_addr = 0x374,
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+ .csid_rdi_format_measure0_addr = 0x378,
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+ .csid_rdi_format_measure1_addr = 0x37c,
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+ .csid_rdi_format_measure2_addr = 0x380,
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+ .csid_rdi_timestamp_curr0_sof_addr = 0x390,
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+ .csid_rdi_timestamp_curr1_sof_addr = 0x394,
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+ .csid_rdi_timestamp_prev0_sof_addr = 0x398,
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+ .csid_rdi_timestamp_prev1_sof_addr = 0x39c,
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+ .csid_rdi_timestamp_curr0_eof_addr = 0x3a0,
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+ .csid_rdi_timestamp_curr1_eof_addr = 0x3a4,
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+ .csid_rdi_timestamp_prev0_eof_addr = 0x3a8,
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+ .csid_rdi_timestamp_prev1_eof_addr = 0x3ac,
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+ .csid_rdi_err_recovery_cfg0_addr = 0x3b0,
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+ .csid_rdi_err_recovery_cfg1_addr = 0x3b4,
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+ .csid_rdi_err_recovery_cfg2_addr = 0x3b8,
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+ .csid_rdi_byte_cntr_ping_addr = 0x3e0,
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+ .csid_rdi_byte_cntr_pong_addr = 0x3e4,
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+ .csid_rdi_multi_vcdt_cfg0_addr = 0x3bc,
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+
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+ /* configurations */
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+ .is_multi_vc_dt_supported = true,
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+ .format_measure_en_shift_val = 0,
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+ .measure_en_hbi_vbi_cnt_val = 0xc,
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+};
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+
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+static struct cam_tfe_csid_rdi_reg_offset cam_tfe_csid_770_rdi_1_reg_offset = {
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+ .csid_rdi_irq_status_addr = 0x50,
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+ .csid_rdi_irq_mask_addr = 0x54,
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+ .csid_rdi_irq_clear_addr = 0x58,
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+ .csid_rdi_irq_set_addr = 0x5c,
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+
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+ .csid_rdi_cfg0_addr = 0x400,
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+ .csid_rdi_cfg1_addr = 0x404,
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+ .csid_rdi_ctrl_addr = 0x408,
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+ .csid_rdi_frame_drop_pattern = 0x40c,
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+ .csid_rdi_frame_drop_period = 0x410,
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+ .csid_rdi_irq_subsample_pattern = 0x414,
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+ .csid_rdi_irq_subsample_period = 0x418,
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+ .csid_rdi_rst_strobes_addr = 0x440,
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+ .csid_rdi_status_addr = 0x450,
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+ .csid_rdi_misr_val0_addr = 0x454,
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+ .csid_rdi_misr_val1_addr = 0x458,
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+ .csid_rdi_misr_val2_addr = 0x45c,
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+ .csid_rdi_misr_val3_addr = 0x460,
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+ .csid_rdi_format_measure_cfg0_addr = 0x470,
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+ .csid_rdi_format_measure_cfg1_addr = 0x474,
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+ .csid_rdi_format_measure0_addr = 0x478,
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+ .csid_rdi_format_measure1_addr = 0x47c,
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+ .csid_rdi_format_measure2_addr = 0x480,
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+ .csid_rdi_timestamp_curr0_sof_addr = 0x490,
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+ .csid_rdi_timestamp_curr1_sof_addr = 0x494,
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+ .csid_rdi_timestamp_prev0_sof_addr = 0x498,
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+ .csid_rdi_timestamp_prev1_sof_addr = 0x49c,
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+ .csid_rdi_timestamp_curr0_eof_addr = 0x4a0,
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+ .csid_rdi_timestamp_curr1_eof_addr = 0x4a4,
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+ .csid_rdi_timestamp_prev0_eof_addr = 0x4a8,
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+ .csid_rdi_timestamp_prev1_eof_addr = 0x4ac,
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+ .csid_rdi_err_recovery_cfg0_addr = 0x4b0,
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+ .csid_rdi_err_recovery_cfg1_addr = 0x4b4,
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+ .csid_rdi_err_recovery_cfg2_addr = 0x4b8,
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+ .csid_rdi_byte_cntr_ping_addr = 0x4e0,
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+ .csid_rdi_byte_cntr_pong_addr = 0x4e4,
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+ .csid_rdi_multi_vcdt_cfg0_addr = 0x4bc,
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+
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+ /* configurations */
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+ .is_multi_vc_dt_supported = true,
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+ .format_measure_en_shift_val = 0,
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+ .measure_en_hbi_vbi_cnt_val = 0xc,
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+};
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+
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+static struct cam_tfe_csid_rdi_reg_offset cam_tfe_csid_770_rdi_2_reg_offset = {
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+ .csid_rdi_irq_status_addr = 0x60,
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+ .csid_rdi_irq_mask_addr = 0x64,
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+ .csid_rdi_irq_clear_addr = 0x68,
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+ .csid_rdi_irq_set_addr = 0x6c,
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+
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+ .csid_rdi_cfg0_addr = 0x500,
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+ .csid_rdi_cfg1_addr = 0x504,
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+ .csid_rdi_ctrl_addr = 0x508,
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+ .csid_rdi_frame_drop_pattern = 0x50c,
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+ .csid_rdi_frame_drop_period = 0x510,
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+ .csid_rdi_irq_subsample_pattern = 0x514,
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+ .csid_rdi_irq_subsample_period = 0x518,
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+ .csid_rdi_rst_strobes_addr = 0x540,
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+ .csid_rdi_status_addr = 0x550,
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+ .csid_rdi_misr_val0_addr = 0x554,
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+ .csid_rdi_misr_val1_addr = 0x558,
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+ .csid_rdi_misr_val2_addr = 0x55c,
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+ .csid_rdi_misr_val3_addr = 0x560,
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+ .csid_rdi_format_measure_cfg0_addr = 0x570,
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+ .csid_rdi_format_measure_cfg1_addr = 0x574,
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+ .csid_rdi_format_measure0_addr = 0x578,
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+ .csid_rdi_format_measure1_addr = 0x57c,
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+ .csid_rdi_format_measure2_addr = 0x580,
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+ .csid_rdi_timestamp_curr0_sof_addr = 0x590,
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+ .csid_rdi_timestamp_curr1_sof_addr = 0x594,
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+ .csid_rdi_timestamp_prev0_sof_addr = 0x598,
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+ .csid_rdi_timestamp_prev1_sof_addr = 0x59c,
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+ .csid_rdi_timestamp_curr0_eof_addr = 0x5a0,
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+ .csid_rdi_timestamp_curr1_eof_addr = 0x5a4,
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+ .csid_rdi_timestamp_prev0_eof_addr = 0x5a8,
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+ .csid_rdi_timestamp_prev1_eof_addr = 0x5ac,
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+ .csid_rdi_err_recovery_cfg0_addr = 0x5b0,
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+ .csid_rdi_err_recovery_cfg1_addr = 0x5b4,
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+ .csid_rdi_err_recovery_cfg2_addr = 0x5b8,
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+ .csid_rdi_byte_cntr_ping_addr = 0x5e0,
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+ .csid_rdi_byte_cntr_pong_addr = 0x5e4,
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+ .csid_rdi_multi_vcdt_cfg0_addr = 0x5bc,
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+
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+ /* configurations */
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+ .is_multi_vc_dt_supported = true,
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+ .format_measure_en_shift_val = 0,
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+ .measure_en_hbi_vbi_cnt_val = 0xc,
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+};
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+
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+static struct cam_tfe_csid_csi2_rx_reg_offset
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+ cam_tfe_csid_770_csi2_reg_offset = {
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+ .csid_csi2_rx_irq_status_addr = 0x20,
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+ .csid_csi2_rx_irq_mask_addr = 0x24,
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+ .csid_csi2_rx_irq_clear_addr = 0x28,
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+ .csid_csi2_rx_irq_set_addr = 0x2c,
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+
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+ /*CSI2 rx control */
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+ .phy_sel_base = 1,
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+ .csid_csi2_rx_cfg0_addr = 0x100,
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+ .csid_csi2_rx_cfg1_addr = 0x104,
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+ .csid_csi2_rx_capture_ctrl_addr = 0x108,
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+ .csid_csi2_rx_rst_strobes_addr = 0x110,
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+ .csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr = 0x120,
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+ .csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr = 0x124,
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+ .csid_csi2_rx_captured_short_pkt_0_addr = 0x128,
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+ .csid_csi2_rx_captured_short_pkt_1_addr = 0x12c,
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+ .csid_csi2_rx_captured_long_pkt_0_addr = 0x130,
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+ .csid_csi2_rx_captured_long_pkt_1_addr = 0x134,
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+ .csid_csi2_rx_captured_long_pkt_ftr_addr = 0x138,
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+ .csid_csi2_rx_captured_cphy_pkt_hdr_addr = 0x13c,
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+ .csid_csi2_rx_total_pkts_rcvd_addr = 0x160,
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+ .csid_csi2_rx_stats_ecc_addr = 0x164,
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+ .csid_csi2_rx_total_crc_err_addr = 0x168,
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+
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+ .phy_tpg_base_id = 0,
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+ .csi2_rst_srb_all = 0x3FFF,
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+ .csi2_rst_done_shift_val = 27,
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+ .csi2_irq_mask_all = 0xFFFFFFF,
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+ .csi2_misr_enable_shift_val = 6,
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+ .csi2_capture_long_pkt_en_shift = 0,
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+ .csi2_capture_short_pkt_en_shift = 1,
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+ .csi2_capture_cphy_pkt_en_shift = 2,
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+ .csi2_capture_long_pkt_dt_shift = 4,
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+ .csi2_capture_long_pkt_vc_shift = 10,
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+ .csi2_capture_short_pkt_vc_shift = 12,
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+ .csi2_capture_cphy_pkt_dt_shift = 14,
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+ .csi2_capture_cphy_pkt_vc_shift = 20,
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+ .csi2_rx_phy_num_mask = 0x7,
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+ .csi2_rx_long_pkt_hdr_rst_stb_shift = 0x1,
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+ .csi2_rx_short_pkt_hdr_rst_stb_shift = 0x2,
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+ .csi2_rx_cphy_pkt_hdr_rst_stb_shift = 0x3,
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+};
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+
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+static struct cam_tfe_csid_common_reg_offset
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+ cam_tfe_csid_770_cmn_reg_offset = {
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+ .csid_hw_version_addr = 0x0,
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+ .csid_cfg0_addr = 0x4,
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+ .csid_ctrl_addr = 0x8,
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+ .csid_rst_strobes_addr = 0x10,
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+
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+ .csid_test_bus_ctrl_addr = 0x14,
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+ .csid_top_irq_status_addr = 0x70,
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+ .csid_top_irq_mask_addr = 0x74,
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+ .csid_top_irq_clear_addr = 0x78,
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+ .csid_top_irq_set_addr = 0x7c,
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+ .csid_irq_cmd_addr = 0x80,
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+
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+ /*configurations */
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+ .major_version = 5,
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+ .minor_version = 3,
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+ .version_incr = 0,
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+ .num_rdis = 3,
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+ .num_pix = 1,
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+ .num_ppp = 1,
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+ .csid_reg_rst_stb = 1,
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+ .csid_rst_stb = 0x1e,
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+ .csid_rst_stb_sw_all = 0x1f,
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+ .ipp_path_rst_stb_all = 0x17,
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+ .ppp_path_rst_stb_all = 0x17,
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+ .rdi_path_rst_stb_all = 0x97,
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+ .path_rst_done_shift_val = 1,
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+ .path_en_shift_val = 31,
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+ .dt_id_shift_val = 27,
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+ .vc_shift_val = 22,
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+ .dt_shift_val = 16,
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+ .vc1_shift_val = 2,
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+ .dt1_shift_val = 7,
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+ .multi_vc_dt_en_shift_val = 0,
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|
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+ .fmt_shift_val = 12,
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+ .plain_fmt_shit_val = 10,
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|
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+ .crop_v_en_shift_val = 6,
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+ .crop_h_en_shift_val = 5,
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+ .crop_shift = 16,
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|
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+ .ipp_irq_mask_all = 0x3FFFF,
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|
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+ .ppp_irq_mask_all = 0x3FFFF,
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|
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+ .rdi_irq_mask_all = 0x3FFFF,
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+ .top_tfe2_pix_pipe_fuse_reg = 0xFE4,
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|
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+ .top_tfe2_fuse_reg = 0xFE8,
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+ .format_measure_support = true,
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+ .format_measure_height_shift_val = 16,
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+ .format_measure_height_mask_val = 0xe,
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|
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+ .format_measure_width_mask_val = 0x10,
|
|
|
+};
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|
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+
|
|
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+static struct cam_tfe_csid_reg_offset cam_tfe_csid_770_reg_offset = {
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|
|
+ .cmn_reg = &cam_tfe_csid_770_cmn_reg_offset,
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|
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+ .csi2_reg = &cam_tfe_csid_770_csi2_reg_offset,
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|
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+ .ipp_reg = &cam_tfe_csid_770_ipp_reg_offset,
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|
|
+ .ppp_reg = &cam_tfe_csid_770_ppp_reg_offset,
|
|
|
+ .rdi_reg = {
|
|
|
+ &cam_tfe_csid_770_rdi_0_reg_offset,
|
|
|
+ &cam_tfe_csid_770_rdi_1_reg_offset,
|
|
|
+ &cam_tfe_csid_770_rdi_2_reg_offset,
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+static struct cam_tfe_csid_hw_info cam_tfe_csid770_hw_info = {
|
|
|
+ .csid_reg = &cam_tfe_csid_770_reg_offset,
|
|
|
+ .hw_dts_version = CAM_TFE_CSID_VERSION_V770,
|
|
|
+};
|
|
|
+
|
|
|
+#endif /*_CAM_TFE_CSID_770_H_ */
|