qcacmn: DSC-Add search_idx tbl alloc framework

In STA mode ast idx override approach is used. In DSc to use ast idx
Need to configure a search idx register with ast idx and cache set number.

Added needed logic to instantiate search index register and
use it for STA mode in DSC path.

Change-Id: I6b3fb7c01a39b16ff1d473381c6155436fe2b27a
CRs-Fixed: 3375219

dp/wifi3.0/be/dp_be.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -218,6 +218,14 @@ struct dp_ppe_vp_tbl_entry {
 	bool is_configured;
 };
 
+/**
+ * struct dp_ppe_vp_search_idx_tbl_entry - PPE Virtual search table entry
+ * @is_configured: Boolean that the entry is configured.
+ */
+struct dp_ppe_vp_search_idx_tbl_entry {
+	bool is_configured;
+};
+
 /**
  * struct dp_ppe_vp_profile - PPE direct switch profiler per vdev
  * @vp_num: Virtual port number
@@ -288,12 +296,17 @@ struct dp_ppeds_napi {
  * @reo2ppe_ring: REO2PPE ring
  * @ppe2tcl_ring: PPE2TCL ring
  * @ppe_vp_tbl: PPE VP table
+ * @ppe_vp_search_idx_tbl: PPE VP search idx table
  * @ppe_vp_tbl_lock: PPE VP table lock
  * @num_ppe_vp_entries : Number of PPE VP entries
  * @ipa_bank_id: TCL bank id used by IPA
  * @ppeds_tx_cc_ctx: Cookie conversion context for ppeds tx desc pool
  * @ppeds_tx_desc: PPEDS tx desc pool
  * @ppeds_handle: PPEDS soc instance handle
+ * @ppe_vp_tbl_lock: PPEDS VP table lock
+ * @num_ppe_vp_entries: PPEDS number of VP entries
+ * @num_ppe_vp_search_idx_entries: PPEDS VP search idx entries
+ * @irq_name: PPEDS VP irq names
  */
 struct dp_soc_be {
 	struct dp_soc soc;
@@ -315,12 +328,14 @@ struct dp_soc_be {
 	struct dp_srng ppe2tcl_ring;
 	struct dp_srng ppeds_wbm_release_ring;
 	struct dp_ppe_vp_tbl_entry *ppe_vp_tbl;
+	struct dp_ppe_vp_search_idx_tbl_entry *ppe_vp_search_idx_tbl;
 	struct dp_hw_cookie_conversion_t ppeds_tx_cc_ctx;
 	struct dp_ppeds_tx_desc_pool_s ppeds_tx_desc;
 	struct dp_ppeds_napi ppeds_napi_ctxt;
 	void *ppeds_handle;
 	qdf_mutex_t ppe_vp_tbl_lock;
 	uint8_t num_ppe_vp_entries;
+	uint8_t num_ppe_vp_search_idx_entries;
 	char irq_name[DP_PPE_INTR_MAX][DP_PPE_INTR_STRNG_LEN];
 #endif
 #ifdef WLAN_FEATURE_11BE_MLO

hal/wifi3.0/be/hal_be_tx.h

@@ -832,7 +832,7 @@ hal_tx_mcast_mlo_reinject_routing_set(
 }
 #endif
 
-/*
+/**
  * hal_reo_config_reo2ppe_dest_info() - Configure reo2ppe dest info
  * @hal_soc_hdl: HAL SoC Context
  *
@@ -847,7 +847,7 @@ void hal_reo_config_reo2ppe_dest_info(hal_soc_handle_t hal_soc_hdl)
 		hal_soc->ops->hal_reo_config_reo2ppe_dest_info(hal_soc_hdl);
 }
 
-/*
+/**
  * hal_tx_get_num_ppe_vp_tbl_entries() - Get the total number of VP table
  * @hal_soc: HAL SoC Context
  *
@@ -861,6 +861,20 @@ uint32_t hal_tx_get_num_ppe_vp_tbl_entries(hal_soc_handle_t hal_soc_hdl)
 	return hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries(hal_soc_hdl);
 }
 
+/**
+ * hal_tx_get_num_ppe_vp_search_idx_tbl_entries() - Get the total number of search idx registers
+ * @hal_soc: HAL SoC Context
+ *
+ * Return: Total number of entries.
+ */
+static inline
+uint32_t hal_tx_get_num_ppe_vp_search_idx_tbl_entries(hal_soc_handle_t hal_soc_hdl)
+{
+	struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
+
+	return hal_soc->ops->hal_tx_get_num_ppe_vp_search_idx_tbl_entries(hal_soc_hdl);
+}
+
 /**
  * hal_tx_set_ppe_cmn_cfg()- Set the PPE common config
  * @hal_soc: HAL SoC context

hal/wifi3.0/hal_internal.h

@@ -1301,6 +1301,8 @@ struct hal_hw_txrx_ops {
 	void (*hal_tx_ring_halt_set)(hal_soc_handle_t hal_soc_hdl);
 	void (*hal_tx_ring_halt_reset)(hal_soc_handle_t hal_soc_hdl);
 	bool (*hal_tx_ring_halt_poll)(hal_soc_handle_t hal_soc_hdl);
+	uint32_t (*hal_tx_get_num_ppe_vp_search_idx_tbl_entries)(
+					hal_soc_handle_t hal_soc_hdl);
 };
 
 /**

hal/wifi3.0/qcn9224/hal_9224.h

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  *
  * Permission to use, copy, modify, and/or distribute this software for
  * any purpose with or without fee is hereby granted, provided that the
@@ -214,6 +214,8 @@ static void hal_get_tqm_scratch_reg_qcn9224(hal_soc_handle_t hal_soc_hdl,
 
 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
 #define HAL_PPE_VP_ENTRIES_MAX 32
+#define HAL_PPE_VP_SEARCH_IDX_REG_MAX 8
+
 /**
  * hal_get_link_desc_size_9224(): API to get the link desc size
  *
@@ -1511,7 +1513,7 @@ static uint32_t hal_qcn9224_get_reo_qdesc_size(uint32_t ba_window_size, int tid)
 }
 
 /*
- * hal_tx_dump_ppe_vp_entry_9224()
+ * hal_tx_get_num_ppe_vp_tbl_entries_9224()
  * @hal_soc_hdl: HAL SoC handle
  *
  * Return: Number of PPE VP entries
@@ -1522,6 +1524,18 @@ uint32_t hal_tx_get_num_ppe_vp_tbl_entries_9224(hal_soc_handle_t hal_soc_hdl)
 	return HAL_PPE_VP_ENTRIES_MAX;
 }
 
+/*
+ * hal_tx_get_num_ppe_vp_search_idx_reg_entries_9224()
+ * @hal_soc_hdl: HAL SoC handle
+ *
+ * Return: Number of PPE VP search index registers
+ */
+static
+uint32_t hal_tx_get_num_ppe_vp_search_idx_reg_entries_9224(hal_soc_handle_t hal_soc_hdl)
+{
+	return HAL_PPE_VP_SEARCH_IDX_REG_MAX;
+}
+
 /**
  * hal_rx_tlv_msdu_done_copy_get_9224() - Get msdu done copy bit from rx_tlv
  *
@@ -1817,6 +1831,8 @@ static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc)
 					hal_tx_ppe2tcl_ring_halt_reset_9224;
 	hal_soc->ops->hal_tx_ring_halt_poll =
 					hal_tx_ppe2tcl_ring_halt_done_9224;
+	hal_soc->ops->hal_tx_get_num_ppe_vp_search_idx_tbl_entries =
+			hal_tx_get_num_ppe_vp_search_idx_reg_entries_9224;
 };
 
 /**