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asoc: codec: add support for wcd939x for pineapple target

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Update wcd939x api and marcro in pineapple driver
Update wcd939x macro in wcd939x driver.

Change-Id: Id87fc550e0a3aff61efee61644fd6bc15ea7c66d
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
This commit is contained in:
Prasad Kumpatla
2022-08-01 22:27:09 +05:30
committed by Gerrit - the friendly Code Review server
vanhempi e8212650cb
commit 23b1088e9f
21 muutettua tiedostoa jossa 13813 lisäystä ja 14 poistoa
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121
asoc/codecs/wcd939x/Kbuild Normal file
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# We can build either as part of a standalone Kernel build or as
# an external module. Determine which mechanism is being used
ifeq ($(MODNAME),)
KERNEL_BUILD := 1
else
KERNEL_BUILD := 0
endif
ifeq ($(KERNEL_BUILD), 1)
# These are configurable via Kconfig for kernel-based builds
# Need to explicitly configure for Android-based builds
AUDIO_BLD_DIR := $(shell pwd)/kernel/msm-5.4
AUDIO_ROOT := $(AUDIO_BLD_DIR)/techpack/audio
endif
ifeq ($(KERNEL_BUILD), 0)
ifeq ($(CONFIG_ARCH_KONA), y)
include $(AUDIO_ROOT)/config/konaauto.conf
INCS += -include $(AUDIO_ROOT)/config/konaautoconf.h
endif
ifeq ($(CONFIG_ARCH_LITO), y)
include $(AUDIO_ROOT)/config/litoauto.conf
export
INCS += -include $(AUDIO_ROOT)/config/litoautoconf.h
endif
ifeq ($(CONFIG_ARCH_WAIPIO), y)
include $(AUDIO_ROOT)/config/waipioauto.conf
INCS += -include $(AUDIO_ROOT)/config/waipioautoconf.h
endif
ifeq ($(CONFIG_ARCH_KALAMA), y)
include $(AUDIO_ROOT)/config/kalamaauto.conf
INCS += -include $(AUDIO_ROOT)/config/kalamaautoconf.h
endif
ifeq ($(CONFIG_ARCH_PINEAPPLE), y)
include $(AUDIO_ROOT)/config/pineappleauto.conf
INCS += -include $(AUDIO_ROOT)/config/pineappleautoconf.h
endif
endif
# As per target team, build is done as follows:
# Defconfig : build with default flags
# Slub : defconfig + CONFIG_SLUB_DEBUG := y +
# CONFIG_SLUB_DEBUG_ON := y + CONFIG_PAGE_POISONING := y
# Perf : Using appropriate msmXXXX-perf_defconfig
#
# Shipment builds (user variants) should not have any debug feature
# enabled. This is identified using 'TARGET_BUILD_VARIANT'. Slub builds
# are identified using the CONFIG_SLUB_DEBUG_ON configuration. Since
# there is no other way to identify defconfig builds, QTI internal
# representation of perf builds (identified using the string 'perf'),
# is used to identify if the build is a slub or defconfig one. This
# way no critical debug feature will be enabled for perf and shipment
# builds. Other OEMs are also protected using the TARGET_BUILD_VARIANT
# config.
############ UAPI ############
UAPI_DIR := uapi/audio
UAPI_INC := -I$(AUDIO_ROOT)/include/$(UAPI_DIR)
############ COMMON ############
COMMON_DIR := include
COMMON_INC := -I$(AUDIO_ROOT)/$(COMMON_DIR)
############ WCD939X ############
# for WCD939X Codec
ifdef CONFIG_SND_SOC_WCD939X
WCD939X_OBJS += wcd939x.o
WCD939X_OBJS += wcd939x-regmap.o
WCD939X_OBJS += wcd939x-tables.o
WCD939X_OBJS += wcd939x-mbhc.o
endif
ifdef CONFIG_SND_SOC_WCD939X_SLAVE
WCD939X_SLAVE_OBJS += wcd939x-slave.o
endif
LINUX_INC += -Iinclude/linux
INCS += $(COMMON_INC) \
$(UAPI_INC)
EXTRA_CFLAGS += $(INCS)
CDEFINES += -DANI_LITTLE_BYTE_ENDIAN \
-DANI_LITTLE_BIT_ENDIAN \
-DDOT11F_LITTLE_ENDIAN_HOST \
-DANI_COMPILER_TYPE_GCC \
-DANI_OS_TYPE_ANDROID=6 \
-DPTT_SOCK_SVC_ENABLE \
-Wall\
-Werror\
-D__linux__
KBUILD_CPPFLAGS += $(CDEFINES)
# Currently, for versions of gcc which support it, the kernel Makefile
# is disabling the maybe-uninitialized warning. Re-enable it for the
# AUDIO driver. Note that we must use EXTRA_CFLAGS here so that it
# will override the kernel settings.
ifeq ($(call cc-option-yn, -Wmaybe-uninitialized),y)
EXTRA_CFLAGS += -Wmaybe-uninitialized
endif
#EXTRA_CFLAGS += -Wmissing-prototypes
ifeq ($(call cc-option-yn, -Wheader-guard),y)
EXTRA_CFLAGS += -Wheader-guard
endif
# Module information used by KBuild framework
obj-$(CONFIG_SND_SOC_WCD939X) += wcd939x_dlkm.o
wcd939x_dlkm-y := $(WCD939X_OBJS)
obj-$(CONFIG_SND_SOC_WCD939X_SLAVE) += wcd939x_slave_dlkm.o
wcd939x_slave_dlkm-y := $(WCD939X_SLAVE_OBJS)
# inject some build related information
DEFINES += -DBUILD_TIMESTAMP=\"$(shell date -u +'%Y-%m-%dT%H:%M:%SZ')\"

6
asoc/codecs/wcd939x/Makefile Normal file
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modules:
$(MAKE) -C $(KERNEL_SRC) M=$(M) modules $(KBUILD_OPTIONS) VERBOSE=1
modules_install:
$(MAKE) M=$(M) -C $(KERNEL_SRC) modules_install
clean:
$(MAKE) -C $(KERNEL_SRC) M=$(M) clean

190
asoc/codecs/wcd939x/internal.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
*/
#ifndef _WCD939X_INTERNAL_H
#define _WCD939X_INTERNAL_H
#include <asoc/wcd-mbhc-v2.h>
#include <asoc/wcd-irq.h>
#include <asoc/wcd-clsh.h>
#include <soc/soundwire.h>
#include "wcd939x-mbhc.h"
#include "wcd939x.h"
#define SWR_SCP_CONTROL 0x44
#define SWR_SCP_HOST_CLK_DIV2_CTL_BANK 0xE0
#define WCD939X_MAX_MICBIAS 4
/* Convert from vout ctl to micbias voltage in mV */
#define WCD_VOUT_CTL_TO_MICB(v) (1000 + v * 50)
#define MAX_PORT 8
#define MAX_CH_PER_PORT 8
#define TX_ADC_MAX 4
#define SWR_NUM_PORTS 4
enum {
TX_HDR12 = 0,
TX_HDR34,
TX_HDR_MAX,
};
extern struct regmap_config wcd939x_regmap_config;
struct codec_port_info {
u32 slave_port_type;
u32 master_port_type;
u32 ch_mask;
u32 num_ch;
u32 ch_rate;
};
struct wcd939x_priv {
struct device *dev;
int variant;
struct snd_soc_component *component;
struct device_node *rst_np;
struct regmap *regmap;
struct swr_device *rx_swr_dev;
struct swr_device *tx_swr_dev;
s32 micb_ref[WCD939X_MAX_MICBIAS];
s32 pullup_ref[WCD939X_MAX_MICBIAS];
struct fw_info *fw_data;
struct device_node *wcd_rst_np;
struct mutex micb_lock;
struct mutex wakeup_lock;
s32 dmic_0_1_clk_cnt;
s32 dmic_2_3_clk_cnt;
s32 dmic_4_5_clk_cnt;
s32 dmic_6_7_clk_cnt;
int hdr_en[TX_HDR_MAX];
/* class h specific info */
struct wcd_clsh_cdc_info clsh_info;
/* mbhc module */
struct wcd939x_mbhc *mbhc;
u32 hph_mode;
u32 tx_mode[TX_ADC_MAX];
s32 adc_count;
bool comp1_enable;
bool comp2_enable;
bool ldoh;
bool bcs_dis;
bool dapm_bias_off;
struct irq_domain *virq;
struct wcd_irq_info irq_info;
u32 rx_clk_cnt;
int num_irq_regs;
/* to track the status */
unsigned long status_mask;
u8 num_tx_ports;
u8 num_rx_ports;
struct codec_port_info
tx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
struct codec_port_info
rx_port_mapping[MAX_PORT][MAX_CH_PER_PORT];
struct swr_port_params tx_port_params[SWR_UC_MAX][SWR_NUM_PORTS];
struct swr_dev_frame_config swr_tx_port_params[SWR_UC_MAX];
struct regulator_bulk_data *supplies;
struct notifier_block nblock;
/* wcd callback to bolero */
void *handle;
int (*update_wcd_event)(void *handle, u16 event, u32 data);
int (*register_notifier)(void *handle,
struct notifier_block *nblock,
bool enable);
int (*wakeup)(void *handle, bool enable);
u32 version;
/* Entry for version info */
struct snd_info_entry *entry;
struct snd_info_entry *version_entry;
struct snd_info_entry *variant_entry;
int flyback_cur_det_disable;
int ear_rx_path;
bool dev_up;
u8 tx_master_ch_map[WCD939X_MAX_SLAVE_CH_TYPES];
bool usbc_hs_status;
/* wcd to swr dmic notification */
bool notify_swr_dmic;
struct blocking_notifier_head notifier;
};
struct wcd939x_micbias_setting {
u8 ldoh_v;
u32 cfilt1_mv;
u32 micb1_mv;
u32 micb2_mv;
u32 micb3_mv;
u32 micb4_mv;
u8 bias1_cfilt_sel;
};
struct wcd939x_pdata {
struct device_node *rst_np;
struct device_node *rx_slave;
struct device_node *tx_slave;
struct wcd939x_micbias_setting micbias;
struct cdc_regulator *regulator;
int num_supplies;
};
struct wcd_ctrl_platform_data {
void *handle;
int (*update_wcd_event)(void *handle, u16 event, u32 data);
int (*register_notifier)(void *handle,
struct notifier_block *nblock,
bool enable);
};
enum {
WCD_RX1,
WCD_RX2,
WCD_RX3
};
enum {
/* INTR_CTRL_INT_MASK_0 */
WCD939X_IRQ_MBHC_BUTTON_PRESS_DET = 0,
WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET,
WCD939X_IRQ_MBHC_ELECT_INS_REM_DET,
WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
WCD939X_IRQ_MBHC_SW_DET,
WCD939X_IRQ_HPHR_OCP_INT,
WCD939X_IRQ_HPHR_CNP_INT,
WCD939X_IRQ_HPHL_OCP_INT,
/* INTR_CTRL_INT_MASK_1 */
WCD939X_IRQ_HPHL_CNP_INT,
WCD939X_IRQ_EAR_CNP_INT,
WCD939X_IRQ_EAR_SCD_INT,
WCD939X_IRQ_HPHL_PDM_WD_INT,
WCD939X_IRQ_HPHR_PDM_WD_INT,
WCD939X_IRQ_EAR_PDM_WD_INT,
/* INTR_CTRL_INT_MASK_2 */
WCD939X_IRQ_LDORT_SCD_INT,
WCD939X_IRQ_MBHC_MOISTURE_INT,
WCD939X_IRQ_HPHL_SURGE_DET_INT,
WCD939X_IRQ_HPHR_SURGE_DET_INT,
WCD939X_NUM_IRQS,
};
extern struct wcd939x_mbhc *wcd939x_soc_get_mbhc(
struct snd_soc_component *component);
extern void wcd939x_disable_bcs_before_slow_insert(
struct snd_soc_component *component,
bool bcs_disable);
extern int wcd939x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
int volt, int micb_num);
extern int wcd939x_get_micb_vout_ctl_val(u32 micb_mv);
extern int wcd939x_micbias_control(struct snd_soc_component *component,
int micb_num, int req, bool is_dapm);
#endif /* _WCD939X_INTERNAL_H */

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asoc/codecs/wcd939x/wcd939x-mbhc.c Normal file
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asoc/codecs/wcd939x/wcd939x-mbhc.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __WCD939X_MBHC_H__
#define __WCD939X_MBHC_H__
#include <asoc/wcd-mbhc-v2.h>
struct wcd939x_mbhc {
struct wcd_mbhc wcd_mbhc;
struct blocking_notifier_head notifier;
struct fw_info *fw_data;
};
#if IS_ENABLED(CONFIG_SND_SOC_WCD939X)
extern int wcd939x_mbhc_init(struct wcd939x_mbhc **mbhc,
struct snd_soc_component *component,
struct fw_info *fw_data);
extern void wcd939x_mbhc_hs_detect_exit(struct snd_soc_component *component);
extern int wcd939x_mbhc_hs_detect(struct snd_soc_component *component,
struct wcd_mbhc_config *mbhc_cfg);
extern void wcd939x_mbhc_deinit(struct snd_soc_component *component);
extern void wcd939x_mbhc_ssr_down(struct wcd939x_mbhc *mbhc,
struct snd_soc_component *component);
extern int wcd939x_mbhc_post_ssr_init(struct wcd939x_mbhc *mbhc,
struct snd_soc_component *component);
extern int wcd939x_mbhc_get_impedance(struct wcd939x_mbhc *wcd939x_mbhc,
uint32_t *zl, uint32_t *zr);
#else
static inline int wcd939x_mbhc_init(struct wcd939x_mbhc **mbhc,
struct snd_soc_component *component,
struct fw_info *fw_data)
{
return 0;
}
static inline void wcd939x_mbhc_hs_detect_exit(
struct snd_soc_component *component)
{
}
static inline int wcd939x_mbhc_hs_detect(struct snd_soc_component *component,
struct wcd_mbhc_config *mbhc_cfg)
{
return 0;
}
static inline void wcd939x_mbhc_deinit(struct snd_soc_component *component)
{
}
static inline void wcd939x_mbhc_ssr_down(struct wcd939x_mbhc *mbhc,
struct snd_soc_component *component)
{
}
static inline int wcd939x_mbhc_post_ssr_init(struct wcd939x_mbhc *mbhc,
struct snd_soc_component *component)
{
return 0;
}
static inline int wcd939x_mbhc_get_impedance(struct wcd939x_mbhc *wcd939x_mbhc,
uint32_t *zl, uint32_t *zr)
{
if (zl)
*zl = 0;
if (zr)
*zr = 0;
return -EINVAL;
}
#endif
#endif /* __WCD939X_MBHC_H__ */

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asoc/codecs/wcd939x/wcd939x-reg-masks.h Normal file
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asoc/codecs/wcd939x/wcd939x-reg-shifts.h Normal file
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asoc/codecs/wcd939x/wcd939x-registers.h Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef WCD939X_REGISTERS_H
#define WCD939X_REGISTERS_H
#define WCD939X_BASE 0x2fff
#define WCD939X_REG(reg) (reg - WCD939X_BASE - 1)
enum {
REG_NO_ACCESS,
RD_REG,
WR_REG,
RD_WR_REG
};
#define WCD939X_ANA_BASE (WCD939X_BASE+0x01)
#define WCD939X_ANA_PAGE (WCD939X_ANA_BASE+0x00)
#define WCD939X_BIAS (WCD939X_ANA_BASE+0x01)
#define WCD939X_RX_SUPPLIES (WCD939X_ANA_BASE+0x08)
#define WCD939X_HPH (WCD939X_ANA_BASE+0x09)
#define WCD939X_EAR (WCD939X_ANA_BASE+0x0a)
#define WCD939X_EAR_COMPANDER_CTL (WCD939X_ANA_BASE+0x0b)
#define WCD939X_TX_CH1 (WCD939X_ANA_BASE+0x0e)
#define WCD939X_TX_CH2 (WCD939X_ANA_BASE+0x0f)
#define WCD939X_TX_CH3 (WCD939X_ANA_BASE+0x10)
#define WCD939X_TX_CH4 (WCD939X_ANA_BASE+0x11)
#define WCD939X_MICB1_MICB2_DSP_EN_LOGIC (WCD939X_ANA_BASE+0x12)
#define WCD939X_MICB3_DSP_EN_LOGIC (WCD939X_ANA_BASE+0x13)
#define WCD939X_MBHC_MECH (WCD939X_ANA_BASE+0x14)
#define WCD939X_MBHC_ELECT (WCD939X_ANA_BASE+0x15)
#define WCD939X_MBHC_ZDET (WCD939X_ANA_BASE+0x16)
#define WCD939X_MBHC_RESULT_1 (WCD939X_ANA_BASE+0x17)
#define WCD939X_MBHC_RESULT_2 (WCD939X_ANA_BASE+0x18)
#define WCD939X_MBHC_RESULT_3 (WCD939X_ANA_BASE+0x19)
#define WCD939X_MBHC_BTN0 (WCD939X_ANA_BASE+0x1a)
#define WCD939X_MBHC_BTN1 (WCD939X_ANA_BASE+0x1b)
#define WCD939X_MBHC_BTN2 (WCD939X_ANA_BASE+0x1c)
#define WCD939X_MBHC_BTN3 (WCD939X_ANA_BASE+0x1d)
#define WCD939X_MBHC_BTN4 (WCD939X_ANA_BASE+0x1e)
#define WCD939X_MBHC_BTN5 (WCD939X_ANA_BASE+0x1f)
#define WCD939X_MBHC_BTN6 (WCD939X_ANA_BASE+0x20)
#define WCD939X_MBHC_BTN7 (WCD939X_ANA_BASE+0x21)
#define WCD939X_MICB1 (WCD939X_ANA_BASE+0x22)
#define WCD939X_MICB2 (WCD939X_ANA_BASE+0x23)
#define WCD939X_MICB2_RAMP (WCD939X_ANA_BASE+0x24)
#define WCD939X_MICB3 (WCD939X_ANA_BASE+0x25)
#define WCD939X_MICB4 (WCD939X_ANA_BASE+0x26)
#define WCD939X_BIAS_BASE (WCD939X_BASE+0x29)
#define WCD939X_CTL (WCD939X_BIAS_BASE+0x00)
#define WCD939X_VBG_FINE_ADJ (WCD939X_BIAS_BASE+0x01)
#define WCD939X_LDOL_BASE (WCD939X_BASE+0x41)
#define WCD939X_VDDCX_ADJUST (WCD939X_LDOL_BASE+0x00)
#define WCD939X_DISABLE_LDOL (WCD939X_LDOL_BASE+0x01)
#define WCD939X_MBHC_BASE (WCD939X_BASE+0x57)
#define WCD939X_CTL_CLK (WCD939X_MBHC_BASE+0x00)
#define WCD939X_CTL_ANA (WCD939X_MBHC_BASE+0x01)
#define WCD939X_ZDET_VNEG_CTL (WCD939X_MBHC_BASE+0x02)
#define WCD939X_ZDET_BIAS_CTL (WCD939X_MBHC_BASE+0x03)
#define WCD939X_CTL_BCS (WCD939X_MBHC_BASE+0x04)
#define WCD939X_MOISTURE_DET_FSM_STATUS (WCD939X_MBHC_BASE+0x05)
#define WCD939X_TEST_CTL (WCD939X_MBHC_BASE+0x06)
#define WCD939X_LDOH_BASE (WCD939X_BASE+0x68)
#define WCD939X_MODE (WCD939X_LDOH_BASE+0x00)
#define WCD939X_LDOH_BIAS (WCD939X_LDOH_BASE+0x01)
#define WCD939X_STB_LOADS (WCD939X_LDOH_BASE+0x02)
#define WCD939X_SLOWRAMP (WCD939X_LDOH_BASE+0x03)
#define WCD939X_MICB1_BASE (WCD939X_BASE+0x6c)
#define WCD939X_TEST_CTL_1 (WCD939X_MICB1_BASE+0x00)
#define WCD939X_TEST_CTL_2 (WCD939X_MICB1_BASE+0x01)
#define WCD939X_TEST_CTL_3 (WCD939X_MICB1_BASE+0x02)
#define WCD939X_MICB2_BASE (WCD939X_BASE+0x6f)
#define WCD939X_MICB2_TEST_CTL_1 (WCD939X_MICB2_BASE+0x00)
#define WCD939X_MICB2_TEST_CTL_2 (WCD939X_MICB2_BASE+0x01)
#define WCD939X_MICB2_TEST_CTL_3 (WCD939X_MICB2_BASE+0x02)
#define WCD939X_MICB3_BASE (WCD939X_BASE+0x72)
#define WCD939X_MICB3_TEST_CTL_1 (WCD939X_MICB3_BASE+0x00)
#define WCD939X_MICB3_TEST_CTL_2 (WCD939X_MICB3_BASE+0x01)
#define WCD939X_MICB3_TEST_CTL_3 (WCD939X_MICB3_BASE+0x02)
#define WCD939X_MICB4_BASE (WCD939X_BASE+0x75)
#define WCD939X_MICB4_TEST_CTL_1 (WCD939X_MICB4_BASE+0x00)
#define WCD939X_MICB4_TEST_CTL_2 (WCD939X_MICB4_BASE+0x01)
#define WCD939X_MICB4_TEST_CTL_3 (WCD939X_MICB4_BASE+0x02)
#define WCD939X_TX_COM_BASE (WCD939X_BASE+0x78)
#define WCD939X_ADC_VCM (WCD939X_TX_COM_BASE+0x00)
#define WCD939X_BIAS_ATEST (WCD939X_TX_COM_BASE+0x01)
#define WCD939X_SPARE1 (WCD939X_TX_COM_BASE+0x02)
#define WCD939X_SPARE2 (WCD939X_TX_COM_BASE+0x03)
#define WCD939X_TXFE_DIV_CTL (WCD939X_TX_COM_BASE+0x04)
#define WCD939X_TXFE_DIV_START (WCD939X_TX_COM_BASE+0x05)
#define WCD939X_SPARE3 (WCD939X_TX_COM_BASE+0x06)
#define WCD939X_SPARE4 (WCD939X_TX_COM_BASE+0x07)
#define WCD939X_TX_1_2_BASE (WCD939X_BASE+0x80)
#define WCD939X_TEST_EN (WCD939X_TX_1_2_BASE+0x00)
#define WCD939X_ADC_IB (WCD939X_TX_1_2_BASE+0x01)
#define WCD939X_ATEST_REFCTL (WCD939X_TX_1_2_BASE+0x02)
#define WCD939X_TX_1_2_TEST_CTL (WCD939X_TX_1_2_BASE+0x03)
#define WCD939X_TEST_BLK_EN1 (WCD939X_TX_1_2_BASE+0x04)
#define WCD939X_TXFE1_CLKDIV (WCD939X_TX_1_2_BASE+0x05)
#define WCD939X_SAR2_ERR (WCD939X_TX_1_2_BASE+0x06)
#define WCD939X_SAR1_ERR (WCD939X_TX_1_2_BASE+0x07)
#define WCD939X_TX_3_4_BASE (WCD939X_BASE+0x88)
#define WCD939X_TX_3_4_TEST_EN (WCD939X_TX_3_4_BASE+0x00)
#define WCD939X_TX_3_4_ADC_IB (WCD939X_TX_3_4_BASE+0x01)
#define WCD939X_TX_3_4_ATEST_REFCTL (WCD939X_TX_3_4_BASE+0x02)
#define WCD939X_TX_3_4_TEST_CTL (WCD939X_TX_3_4_BASE+0x03)
#define WCD939X_TEST_BLK_EN3 (WCD939X_TX_3_4_BASE+0x04)
#define WCD939X_TXFE3_CLKDIV (WCD939X_TX_3_4_BASE+0x05)
#define WCD939X_SAR4_ERR (WCD939X_TX_3_4_BASE+0x06)
#define WCD939X_SAR3_ERR (WCD939X_TX_3_4_BASE+0x07)
#define WCD939X_TEST_BLK_EN2 (WCD939X_TX_3_4_BASE+0x08)
#define WCD939X_TXFE2_CLKDIV (WCD939X_TX_3_4_BASE+0x09)
#define WCD939X_TX_3_4_SPARE1 (WCD939X_TX_3_4_BASE+0x0a)
#define WCD939X_TEST_BLK_EN4 (WCD939X_TX_3_4_BASE+0x0b)
#define WCD939X_TXFE4_CLKDIV (WCD939X_TX_3_4_BASE+0x0c)
#define WCD939X_TX_3_4_SPARE2 (WCD939X_TX_3_4_BASE+0x0d)
#define WCD939X_CLASSH_BASE (WCD939X_BASE+0x98)
#define WCD939X_MODE_1 (WCD939X_CLASSH_BASE+0x00)
#define WCD939X_MODE_2 (WCD939X_CLASSH_BASE+0x01)
#define WCD939X_MODE_3 (WCD939X_CLASSH_BASE+0x02)
#define WCD939X_CTRL_VCL_1 (WCD939X_CLASSH_BASE+0x03)
#define WCD939X_CTRL_VCL_2 (WCD939X_CLASSH_BASE+0x04)
#define WCD939X_CTRL_CCL_1 (WCD939X_CLASSH_BASE+0x05)
#define WCD939X_CTRL_CCL_2 (WCD939X_CLASSH_BASE+0x06)
#define WCD939X_CTRL_CCL_3 (WCD939X_CLASSH_BASE+0x07)
#define WCD939X_CTRL_CCL_4 (WCD939X_CLASSH_BASE+0x08)
#define WCD939X_CTRL_CCL_5 (WCD939X_CLASSH_BASE+0x09)
#define WCD939X_BUCK_TMUX_A_D (WCD939X_CLASSH_BASE+0x0a)
#define WCD939X_BUCK_SW_DRV_CNTL (WCD939X_CLASSH_BASE+0x0b)
#define WCD939X_SPARE (WCD939X_CLASSH_BASE+0x0c)
#define WCD939X_FLYBACK_BASE (WCD939X_BASE+0xa5)
#define WCD939X_EN (WCD939X_FLYBACK_BASE+0x00)
#define WCD939X_VNEG_CTRL_1 (WCD939X_FLYBACK_BASE+0x01)
#define WCD939X_VNEG_CTRL_2 (WCD939X_FLYBACK_BASE+0x02)
#define WCD939X_VNEG_CTRL_3 (WCD939X_FLYBACK_BASE+0x03)
#define WCD939X_VNEG_CTRL_4 (WCD939X_FLYBACK_BASE+0x04)
#define WCD939X_VNEG_CTRL_5 (WCD939X_FLYBACK_BASE+0x05)
#define WCD939X_VNEG_CTRL_6 (WCD939X_FLYBACK_BASE+0x06)
#define WCD939X_VNEG_CTRL_7 (WCD939X_FLYBACK_BASE+0x07)
#define WCD939X_VNEG_CTRL_8 (WCD939X_FLYBACK_BASE+0x08)
#define WCD939X_VNEG_CTRL_9 (WCD939X_FLYBACK_BASE+0x09)
#define WCD939X_VNEGDAC_CTRL_1 (WCD939X_FLYBACK_BASE+0x0a)
#define WCD939X_VNEGDAC_CTRL_2 (WCD939X_FLYBACK_BASE+0x0b)
#define WCD939X_VNEGDAC_CTRL_3 (WCD939X_FLYBACK_BASE+0x0c)
#define WCD939X_CTRL_1 (WCD939X_FLYBACK_BASE+0x0d)
#define WCD939X_FLYBACK_TEST_CTL (WCD939X_FLYBACK_BASE+0x0e)
#define WCD939X_RX_BASE (WCD939X_BASE+0xb4)
#define WCD939X_AUX_SW_CTL (WCD939X_RX_BASE+0x00)
#define WCD939X_PA_AUX_IN_CONN (WCD939X_RX_BASE+0x01)
#define WCD939X_TIMER_DIV (WCD939X_RX_BASE+0x02)
#define WCD939X_OCP_CTL (WCD939X_RX_BASE+0x03)
#define WCD939X_OCP_COUNT (WCD939X_RX_BASE+0x04)
#define WCD939X_BIAS_EAR_DAC (WCD939X_RX_BASE+0x05)
#define WCD939X_BIAS_EAR_AMP (WCD939X_RX_BASE+0x06)
#define WCD939X_BIAS_HPH_LDO (WCD939X_RX_BASE+0x07)
#define WCD939X_BIAS_HPH_PA (WCD939X_RX_BASE+0x08)
#define WCD939X_BIAS_HPH_RDACBUFF_CNP2 (WCD939X_RX_BASE+0x09)
#define WCD939X_BIAS_HPH_RDAC_LDO (WCD939X_RX_BASE+0x0a)
#define WCD939X_BIAS_HPH_CNP1 (WCD939X_RX_BASE+0x0b)
#define WCD939X_BIAS_HPH_LOWPOWER (WCD939X_RX_BASE+0x0c)
#define WCD939X_BIAS_AUX_DAC (WCD939X_RX_BASE+0x0d)
#define WCD939X_BIAS_AUX_AMP (WCD939X_RX_BASE+0x0e)
#define WCD939X_BIAS_VNEGDAC_BLEEDER (WCD939X_RX_BASE+0x0f)
#define WCD939X_BIAS_MISC (WCD939X_RX_BASE+0x10)
#define WCD939X_BIAS_BUCK_RST (WCD939X_RX_BASE+0x11)
#define WCD939X_BIAS_BUCK_VREF_ERRAMP (WCD939X_RX_BASE+0x12)
#define WCD939X_BIAS_FLYB_ERRAMP (WCD939X_RX_BASE+0x13)
#define WCD939X_BIAS_FLYB_BUFF (WCD939X_RX_BASE+0x14)
#define WCD939X_BIAS_FLYB_MID_RST (WCD939X_RX_BASE+0x15)
#define WCD939X_HPH_BASE (WCD939X_BASE+0xca)
#define WCD939X_L_STATUS (WCD939X_HPH_BASE+0x00)
#define WCD939X_R_STATUS (WCD939X_HPH_BASE+0x01)
#define WCD939X_CNP_EN (WCD939X_HPH_BASE+0x02)
#define WCD939X_CNP_WG_CTL (WCD939X_HPH_BASE+0x03)
#define WCD939X_CNP_WG_TIME (WCD939X_HPH_BASE+0x04)
#define WCD939X_HPH_OCP_CTL (WCD939X_HPH_BASE+0x05)
#define WCD939X_AUTO_CHOP (WCD939X_HPH_BASE+0x06)
#define WCD939X_CHOP_CTL (WCD939X_HPH_BASE+0x07)
#define WCD939X_PA_CTL1 (WCD939X_HPH_BASE+0x08)
#define WCD939X_PA_CTL2 (WCD939X_HPH_BASE+0x09)
#define WCD939X_L_EN (WCD939X_HPH_BASE+0x0a)
#define WCD939X_L_TEST (WCD939X_HPH_BASE+0x0b)
#define WCD939X_L_ATEST (WCD939X_HPH_BASE+0x0c)
#define WCD939X_R_EN (WCD939X_HPH_BASE+0x0d)
#define WCD939X_R_TEST (WCD939X_HPH_BASE+0x0e)
#define WCD939X_R_ATEST (WCD939X_HPH_BASE+0x0f)
#define WCD939X_RDAC_CLK_CTL1 (WCD939X_HPH_BASE+0x10)
#define WCD939X_RDAC_CLK_CTL2 (WCD939X_HPH_BASE+0x11)
#define WCD939X_RDAC_LDO_CTL (WCD939X_HPH_BASE+0x12)
#define WCD939X_RDAC_CHOP_CLK_LP_CTL (WCD939X_HPH_BASE+0x13)
#define WCD939X_REFBUFF_UHQA_CTL (WCD939X_HPH_BASE+0x14)
#define WCD939X_REFBUFF_LP_CTL (WCD939X_HPH_BASE+0x15)
#define WCD939X_L_DAC_CTL (WCD939X_HPH_BASE+0x16)
#define WCD939X_R_DAC_CTL (WCD939X_HPH_BASE+0x17)
#define WCD939X_HPH_SURGE_BASE (WCD939X_BASE+0xe2)
#define WCD939X_HPHLR_SURGE_COMP_SEL (WCD939X_HPH_SURGE_BASE+0x00)
#define WCD939X_HPHLR_SURGE_EN (WCD939X_HPH_SURGE_BASE+0x01)
#define WCD939X_HPHLR_SURGE_MISC1 (WCD939X_HPH_SURGE_BASE+0x02)
#define WCD939X_HPHLR_SURGE_STATUS (WCD939X_HPH_SURGE_BASE+0x03)
#define WCD939X_EAR_BASE (WCD939X_BASE+0xea)
#define WCD939X_EAR_EN_REG (WCD939X_EAR_BASE+0x00)
#define WCD939X_EAR_PA_CON (WCD939X_EAR_BASE+0x01)
#define WCD939X_EAR_SP_CON (WCD939X_EAR_BASE+0x02)
#define WCD939X_EAR_DAC_CON (WCD939X_EAR_BASE+0x03)
#define WCD939X_EAR_CNP_FSM_CON (WCD939X_EAR_BASE+0x04)
#define WCD939X_EAR_TEST_CTL (WCD939X_EAR_BASE+0x05)
#define WCD939X_STATUS_REG_1 (WCD939X_EAR_BASE+0x06)
#define WCD939X_STATUS_REG_2 (WCD939X_EAR_BASE+0x07)
#define WCD939X_ANA_NEW_BASE (WCD939X_BASE+0x101)
#define WCD939X_ANA_NEW_PAGE (WCD939X_ANA_NEW_BASE+0x00)
#define WCD939X_HPH_NEW_BASE (WCD939X_BASE+0x102)
#define WCD939X_ANA_HPH2 (WCD939X_HPH_NEW_BASE+0x00)
#define WCD939X_ANA_HPH3 (WCD939X_HPH_NEW_BASE+0x01)
#define WCD939X_SLEEP_BASE (WCD939X_BASE+0x104)
#define WCD939X_SLEEP_CTL (WCD939X_SLEEP_BASE+0x00)
#define WCD939X_WATCHDOG_CTL (WCD939X_SLEEP_BASE+0x01)
#define WCD939X_MBHC_NEW_BASE (WCD939X_BASE+0x120)
#define WCD939X_ELECT_REM_CLAMP_CTL (WCD939X_MBHC_NEW_BASE+0x00)
#define WCD939X_CTL_1 (WCD939X_MBHC_NEW_BASE+0x01)
#define WCD939X_CTL_2 (WCD939X_MBHC_NEW_BASE+0x02)
#define WCD939X_PLUG_DETECT_CTL (WCD939X_MBHC_NEW_BASE+0x03)
#define WCD939X_ZDET_ANA_CTL (WCD939X_MBHC_NEW_BASE+0x04)
#define WCD939X_ZDET_RAMP_CTL (WCD939X_MBHC_NEW_BASE+0x05)
#define WCD939X_FSM_STATUS (WCD939X_MBHC_NEW_BASE+0x06)
#define WCD939X_ADC_RESULT (WCD939X_MBHC_NEW_BASE+0x07)
#define WCD939X_TX_NEW_BASE (WCD939X_BASE+0x128)
#define WCD939X_TX_CH12_MUX (WCD939X_TX_NEW_BASE+0x00)
#define WCD939X_TX_CH34_MUX (WCD939X_TX_NEW_BASE+0x01)
#define WCD939X_DIE_CRACK_BASE (WCD939X_BASE+0x12d)
#define WCD939X_DIE_CRK_DET_EN (WCD939X_DIE_CRACK_BASE+0x00)
#define WCD939X_DIE_CRK_DET_OUT (WCD939X_DIE_CRACK_BASE+0x01)
#define WCD939X_HPH_NEW_INT_BASE (WCD939X_BASE+0x133)
#define WCD939X_RDAC_GAIN_CTL (WCD939X_HPH_NEW_INT_BASE+0x00)
#define WCD939X_PA_GAIN_CTL_L (WCD939X_HPH_NEW_INT_BASE+0x01)
#define WCD939X_RDAC_VREF_CTL (WCD939X_HPH_NEW_INT_BASE+0x02)
#define WCD939X_RDAC_OVERRIDE_CTL (WCD939X_HPH_NEW_INT_BASE+0x03)
#define WCD939X_PA_GAIN_CTL_R (WCD939X_HPH_NEW_INT_BASE+0x04)
#define WCD939X_PA_MISC1 (WCD939X_HPH_NEW_INT_BASE+0x05)
#define WCD939X_PA_MISC2 (WCD939X_HPH_NEW_INT_BASE+0x06)
#define WCD939X_PA_RDAC_MISC (WCD939X_HPH_NEW_INT_BASE+0x07)
#define WCD939X_HPH_TIMER1 (WCD939X_HPH_NEW_INT_BASE+0x08)
#define WCD939X_HPH_TIMER2 (WCD939X_HPH_NEW_INT_BASE+0x09)
#define WCD939X_HPH_TIMER3 (WCD939X_HPH_NEW_INT_BASE+0x0a)
#define WCD939X_HPH_TIMER4 (WCD939X_HPH_NEW_INT_BASE+0x0b)
#define WCD939X_PA_RDAC_MISC2 (WCD939X_HPH_NEW_INT_BASE+0x0c)
#define WCD939X_PA_RDAC_MISC3 (WCD939X_HPH_NEW_INT_BASE+0x0d)
#define WCD939X_RDAC_HD2_CTL_L (WCD939X_HPH_NEW_INT_BASE+0x0e)
#define WCD939X_RDAC_HD2_CTL_R (WCD939X_HPH_NEW_INT_BASE+0x0f)
#define WCD939X_RX_NEW_INT_BASE (WCD939X_BASE+0x146)
#define WCD939X_HPH_RDAC_BIAS_LOHIFI (WCD939X_RX_NEW_INT_BASE+0x00)
#define WCD939X_HPH_RDAC_BIAS_ULP (WCD939X_RX_NEW_INT_BASE+0x01)
#define WCD939X_HPH_RDAC_LDO_LP (WCD939X_RX_NEW_INT_BASE+0x02)
#define WCD939X_MBHC_NEW_INT_BASE (WCD939X_BASE+0x1b0)
#define WCD939X_MOISTURE_DET_DC_CTRL (WCD939X_MBHC_NEW_INT_BASE+0x00)
#define WCD939X_MOISTURE_DET_POLLING_CTRL (WCD939X_MBHC_NEW_INT_BASE+0x01)
#define WCD939X_MECH_DET_CURRENT (WCD939X_MBHC_NEW_INT_BASE+0x02)
#define WCD939X_ZDET_CLK_AND_MOISTURE_CTL_NEW (WCD939X_MBHC_NEW_INT_BASE+0x03)
#define WCD939X_EAR_INT_NEW_BASE (WCD939X_BASE+0x1b8)
#define WCD939X_EAR_CHOPPER_CON (WCD939X_EAR_INT_NEW_BASE+0x00)
#define WCD939X_CNP_VCM_CON1 (WCD939X_EAR_INT_NEW_BASE+0x01)
#define WCD939X_CNP_VCM_CON2 (WCD939X_EAR_INT_NEW_BASE+0x02)
#define WCD939X_EAR_DYNAMIC_BIAS (WCD939X_EAR_INT_NEW_BASE+0x03)
#define WCD939X_SLEEP_INT_BASE (WCD939X_BASE+0x1d1)
#define WCD939X_WATCHDOG_CTL_1 (WCD939X_SLEEP_INT_BASE+0x00)
#define WCD939X_WATCHDOG_CTL_2 (WCD939X_SLEEP_INT_BASE+0x01)
#define WCD939X_DIE_CRACK_INT_BASE (WCD939X_BASE+0x1d4)
#define WCD939X_DIE_CRK_DET_INT1 (WCD939X_DIE_CRACK_INT_BASE+0x00)
#define WCD939X_DIE_CRK_DET_INT2 (WCD939X_DIE_CRACK_INT_BASE+0x01)
#define WCD939X_TX_COM_NEW_INT_BASE (WCD939X_BASE+0x1d6)
#define WCD939X_TXFE_DIVSTOP_L2 (WCD939X_TX_COM_NEW_INT_BASE+0x00)
#define WCD939X_TXFE_DIVSTOP_L1 (WCD939X_TX_COM_NEW_INT_BASE+0x01)
#define WCD939X_TXFE_DIVSTOP_L0 (WCD939X_TX_COM_NEW_INT_BASE+0x02)
#define WCD939X_TXFE_DIVSTOP_ULP1P2M (WCD939X_TX_COM_NEW_INT_BASE+0x03)
#define WCD939X_TXFE_DIVSTOP_ULP0P6M (WCD939X_TX_COM_NEW_INT_BASE+0x04)
#define WCD939X_TXFE_ICTRL_STG1_L2L1 (WCD939X_TX_COM_NEW_INT_BASE+0x05)
#define WCD939X_TXFE_ICTRL_STG1_L0 (WCD939X_TX_COM_NEW_INT_BASE+0x06)
#define WCD939X_TXFE_ICTRL_STG1_ULP (WCD939X_TX_COM_NEW_INT_BASE+0x07)
#define WCD939X_TXFE_ICTRL_STG2MAIN_L2L1 (WCD939X_TX_COM_NEW_INT_BASE+0x08)
#define WCD939X_TXFE_ICTRL_STG2MAIN_L0 (WCD939X_TX_COM_NEW_INT_BASE+0x09)
#define WCD939X_TXFE_ICTRL_STG2MAIN_ULP (WCD939X_TX_COM_NEW_INT_BASE+0x0a)
#define WCD939X_TXFE_ICTRL_STG2CASC_L2L1L0 (WCD939X_TX_COM_NEW_INT_BASE+0x0b)
#define WCD939X_TXFE_ICTRL_STG2CASC_ULP (WCD939X_TX_COM_NEW_INT_BASE+0x0c)
#define WCD939X_TXADC_SCBIAS_L2L1 (WCD939X_TX_COM_NEW_INT_BASE+0x0d)
#define WCD939X_TXADC_SCBIAS_L0ULP (WCD939X_TX_COM_NEW_INT_BASE+0x0e)
#define WCD939X_TXADC_INT_L2 (WCD939X_TX_COM_NEW_INT_BASE+0x0f)
#define WCD939X_TXADC_INT_L1 (WCD939X_TX_COM_NEW_INT_BASE+0x10)
#define WCD939X_TXADC_INT_L0 (WCD939X_TX_COM_NEW_INT_BASE+0x11)
#define WCD939X_TXADC_INT_ULP (WCD939X_TX_COM_NEW_INT_BASE+0x12)
#define WCD939X_DIGITAL_BASE (WCD939X_BASE+0x401)
#define WCD939X_DIGITAL_PAGE (WCD939X_DIGITAL_BASE+0x00)
#define WCD939X_CHIP_ID0 (WCD939X_DIGITAL_BASE+0x01)
#define WCD939X_CHIP_ID1 (WCD939X_DIGITAL_BASE+0x02)
#define WCD939X_CHIP_ID2 (WCD939X_DIGITAL_BASE+0x03)
#define WCD939X_CHIP_ID3 (WCD939X_DIGITAL_BASE+0x04)
#define WCD939X_SWR_TX_CLK_RATE (WCD939X_DIGITAL_BASE+0x05)
#define WCD939X_CDC_RST_CTL (WCD939X_DIGITAL_BASE+0x06)
#define WCD939X_TOP_CLK_CFG (WCD939X_DIGITAL_BASE+0x07)
#define WCD939X_CDC_ANA_CLK_CTL (WCD939X_DIGITAL_BASE+0x08)
#define WCD939X_CDC_DIG_CLK_CTL (WCD939X_DIGITAL_BASE+0x09)
#define WCD939X_SWR_RST_EN (WCD939X_DIGITAL_BASE+0x0a)
#define WCD939X_CDC_PATH_MODE (WCD939X_DIGITAL_BASE+0x0b)
#define WCD939X_CDC_RX_RST (WCD939X_DIGITAL_BASE+0x0c)
#define WCD939X_CDC_RX0_CTL (WCD939X_DIGITAL_BASE+0x0d)
#define WCD939X_CDC_RX1_CTL (WCD939X_DIGITAL_BASE+0x0e)
#define WCD939X_CDC_RX2_CTL (WCD939X_DIGITAL_BASE+0x0f)
#define WCD939X_CDC_TX_ANA_MODE_0_1 (WCD939X_DIGITAL_BASE+0x10)
#define WCD939X_CDC_TX_ANA_MODE_2_3 (WCD939X_DIGITAL_BASE+0x11)
#define WCD939X_CDC_COMP_CTL_0 (WCD939X_DIGITAL_BASE+0x14)
#define WCD939X_CDC_ANA_TX_CLK_CTL (WCD939X_DIGITAL_BASE+0x17)
#define WCD939X_CDC_HPH_DSM_A1_0 (WCD939X_DIGITAL_BASE+0x18)
#define WCD939X_CDC_HPH_DSM_A1_1 (WCD939X_DIGITAL_BASE+0x19)
#define WCD939X_CDC_HPH_DSM_A2_0 (WCD939X_DIGITAL_BASE+0x1a)
#define WCD939X_CDC_HPH_DSM_A2_1 (WCD939X_DIGITAL_BASE+0x1b)
#define WCD939X_CDC_HPH_DSM_A3_0 (WCD939X_DIGITAL_BASE+0x1c)
#define WCD939X_CDC_HPH_DSM_A3_1 (WCD939X_DIGITAL_BASE+0x1d)
#define WCD939X_CDC_HPH_DSM_A4_0 (WCD939X_DIGITAL_BASE+0x1e)
#define WCD939X_CDC_HPH_DSM_A4_1 (WCD939X_DIGITAL_BASE+0x1f)
#define WCD939X_CDC_HPH_DSM_A5_0 (WCD939X_DIGITAL_BASE+0x20)
#define WCD939X_CDC_HPH_DSM_A5_1 (WCD939X_DIGITAL_BASE+0x21)
#define WCD939X_CDC_HPH_DSM_A6_0 (WCD939X_DIGITAL_BASE+0x22)
#define WCD939X_CDC_HPH_DSM_A7_0 (WCD939X_DIGITAL_BASE+0x23)
#define WCD939X_CDC_HPH_DSM_C_0 (WCD939X_DIGITAL_BASE+0x24)
#define WCD939X_CDC_HPH_DSM_C_1 (WCD939X_DIGITAL_BASE+0x25)
#define WCD939X_CDC_HPH_DSM_C_2 (WCD939X_DIGITAL_BASE+0x26)
#define WCD939X_CDC_HPH_DSM_C_3 (WCD939X_DIGITAL_BASE+0x27)
#define WCD939X_CDC_HPH_DSM_R1 (WCD939X_DIGITAL_BASE+0x28)
#define WCD939X_CDC_HPH_DSM_R2 (WCD939X_DIGITAL_BASE+0x29)
#define WCD939X_CDC_HPH_DSM_R3 (WCD939X_DIGITAL_BASE+0x2a)
#define WCD939X_CDC_HPH_DSM_R4 (WCD939X_DIGITAL_BASE+0x2b)
#define WCD939X_CDC_HPH_DSM_R5 (WCD939X_DIGITAL_BASE+0x2c)
#define WCD939X_CDC_HPH_DSM_R6 (WCD939X_DIGITAL_BASE+0x2d)
#define WCD939X_CDC_HPH_DSM_R7 (WCD939X_DIGITAL_BASE+0x2e)
#define WCD939X_CDC_EAR_DSM_A1_0 (WCD939X_DIGITAL_BASE+0x2f)
#define WCD939X_CDC_EAR_DSM_A1_1 (WCD939X_DIGITAL_BASE+0x30)
#define WCD939X_CDC_EAR_DSM_A2_0 (WCD939X_DIGITAL_BASE+0x31)
#define WCD939X_CDC_EAR_DSM_A2_1 (WCD939X_DIGITAL_BASE+0x32)
#define WCD939X_CDC_EAR_DSM_A3_0 (WCD939X_DIGITAL_BASE+0x33)
#define WCD939X_CDC_EAR_DSM_A3_1 (WCD939X_DIGITAL_BASE+0x34)
#define WCD939X_CDC_EAR_DSM_A4_0 (WCD939X_DIGITAL_BASE+0x35)
#define WCD939X_CDC_EAR_DSM_A4_1 (WCD939X_DIGITAL_BASE+0x36)
#define WCD939X_CDC_EAR_DSM_A5_0 (WCD939X_DIGITAL_BASE+0x37)
#define WCD939X_CDC_EAR_DSM_A5_1 (WCD939X_DIGITAL_BASE+0x38)
#define WCD939X_CDC_EAR_DSM_A6_0 (WCD939X_DIGITAL_BASE+0x39)
#define WCD939X_CDC_EAR_DSM_A7_0 (WCD939X_DIGITAL_BASE+0x3a)
#define WCD939X_CDC_EAR_DSM_C_0 (WCD939X_DIGITAL_BASE+0x3b)
#define WCD939X_CDC_EAR_DSM_C_1 (WCD939X_DIGITAL_BASE+0x3c)
#define WCD939X_CDC_EAR_DSM_C_2 (WCD939X_DIGITAL_BASE+0x3d)
#define WCD939X_CDC_EAR_DSM_C_3 (WCD939X_DIGITAL_BASE+0x3e)
#define WCD939X_CDC_EAR_DSM_R1 (WCD939X_DIGITAL_BASE+0x3f)
#define WCD939X_CDC_EAR_DSM_R2 (WCD939X_DIGITAL_BASE+0x40)
#define WCD939X_CDC_EAR_DSM_R3 (WCD939X_DIGITAL_BASE+0x41)
#define WCD939X_CDC_EAR_DSM_R4 (WCD939X_DIGITAL_BASE+0x42)
#define WCD939X_CDC_EAR_DSM_R5 (WCD939X_DIGITAL_BASE+0x43)
#define WCD939X_CDC_EAR_DSM_R6 (WCD939X_DIGITAL_BASE+0x44)
#define WCD939X_CDC_EAR_DSM_R7 (WCD939X_DIGITAL_BASE+0x45)
#define WCD939X_CDC_HPH_GAIN_RX_0 (WCD939X_DIGITAL_BASE+0x46)
#define WCD939X_CDC_HPH_GAIN_RX_1 (WCD939X_DIGITAL_BASE+0x47)
#define WCD939X_CDC_HPH_GAIN_DSD_0 (WCD939X_DIGITAL_BASE+0x48)
#define WCD939X_CDC_HPH_GAIN_DSD_1 (WCD939X_DIGITAL_BASE+0x49)
#define WCD939X_CDC_HPH_GAIN_DSD_2 (WCD939X_DIGITAL_BASE+0x4a)
#define WCD939X_CDC_EAR_GAIN_DSD_0 (WCD939X_DIGITAL_BASE+0x4b)
#define WCD939X_CDC_EAR_GAIN_DSD_1 (WCD939X_DIGITAL_BASE+0x4c)
#define WCD939X_CDC_EAR_GAIN_DSD_2 (WCD939X_DIGITAL_BASE+0x4d)
#define WCD939X_CDC_HPH_GAIN_CTL (WCD939X_DIGITAL_BASE+0x4e)
#define WCD939X_CDC_EAR_GAIN_CTL (WCD939X_DIGITAL_BASE+0x4f)
#define WCD939X_CDC_EAR_PATH_CTL (WCD939X_DIGITAL_BASE+0x50)
#define WCD939X_CDC_SWR_CLH (WCD939X_DIGITAL_BASE+0x51)
#define WCD939X_SWR_CLH_BYP (WCD939X_DIGITAL_BASE+0x52)
#define WCD939X_CDC_TX0_CTL (WCD939X_DIGITAL_BASE+0x53)
#define WCD939X_CDC_TX1_CTL (WCD939X_DIGITAL_BASE+0x54)
#define WCD939X_CDC_TX2_CTL (WCD939X_DIGITAL_BASE+0x55)
#define WCD939X_CDC_TX_RST (WCD939X_DIGITAL_BASE+0x56)
#define WCD939X_CDC_REQ_CTL (WCD939X_DIGITAL_BASE+0x57)
#define WCD939X_CDC_RST (WCD939X_DIGITAL_BASE+0x58)
#define WCD939X_CDC_AMIC_CTL (WCD939X_DIGITAL_BASE+0x5a)
#define WCD939X_CDC_DMIC_CTL (WCD939X_DIGITAL_BASE+0x5b)
#define WCD939X_CDC_DMIC1_CTL (WCD939X_DIGITAL_BASE+0x5c)
#define WCD939X_CDC_DMIC2_CTL (WCD939X_DIGITAL_BASE+0x5d)
#define WCD939X_CDC_DMIC3_CTL (WCD939X_DIGITAL_BASE+0x5e)
#define WCD939X_CDC_DMIC4_CTL (WCD939X_DIGITAL_BASE+0x5f)
#define WCD939X_EFUSE_PRG_CTL (WCD939X_DIGITAL_BASE+0x60)
#define WCD939X_EFUSE_CTL (WCD939X_DIGITAL_BASE+0x61)
#define WCD939X_CDC_DMIC_RATE_1_2 (WCD939X_DIGITAL_BASE+0x62)
#define WCD939X_CDC_DMIC_RATE_3_4 (WCD939X_DIGITAL_BASE+0x63)
#define WCD939X_PDM_WD_CTL0 (WCD939X_DIGITAL_BASE+0x65)
#define WCD939X_PDM_WD_CTL1 (WCD939X_DIGITAL_BASE+0x66)
#define WCD939X_PDM_WD_CTL2 (WCD939X_DIGITAL_BASE+0x67)
#define WCD939X_INTR_MODE (WCD939X_DIGITAL_BASE+0x6a)
#define WCD939X_INTR_MASK_0 (WCD939X_DIGITAL_BASE+0x6b)
#define WCD939X_INTR_MASK_1 (WCD939X_DIGITAL_BASE+0x6c)
#define WCD939X_INTR_MASK_2 (WCD939X_DIGITAL_BASE+0x6d)
#define WCD939X_INTR_STATUS_0 (WCD939X_DIGITAL_BASE+0x6e)
#define WCD939X_INTR_STATUS_1 (WCD939X_DIGITAL_BASE+0x6f)
#define WCD939X_INTR_STATUS_2 (WCD939X_DIGITAL_BASE+0x70)
#define WCD939X_INTR_CLEAR_0 (WCD939X_DIGITAL_BASE+0x71)
#define WCD939X_INTR_CLEAR_1 (WCD939X_DIGITAL_BASE+0x72)
#define WCD939X_INTR_CLEAR_2 (WCD939X_DIGITAL_BASE+0x73)
#define WCD939X_INTR_LEVEL_0 (WCD939X_DIGITAL_BASE+0x74)
#define WCD939X_INTR_LEVEL_1 (WCD939X_DIGITAL_BASE+0x75)
#define WCD939X_INTR_LEVEL_2 (WCD939X_DIGITAL_BASE+0x76)
#define WCD939X_INTR_SET_0 (WCD939X_DIGITAL_BASE+0x77)
#define WCD939X_INTR_SET_1 (WCD939X_DIGITAL_BASE+0x78)
#define WCD939X_INTR_SET_2 (WCD939X_DIGITAL_BASE+0x79)
#define WCD939X_INTR_TEST_0 (WCD939X_DIGITAL_BASE+0x7a)
#define WCD939X_INTR_TEST_1 (WCD939X_DIGITAL_BASE+0x7b)
#define WCD939X_INTR_TEST_2 (WCD939X_DIGITAL_BASE+0x7c)
#define WCD939X_TX_MODE_DBG_EN (WCD939X_DIGITAL_BASE+0x7f)
#define WCD939X_TX_MODE_DBG_0_1 (WCD939X_DIGITAL_BASE+0x80)
#define WCD939X_TX_MODE_DBG_2_3 (WCD939X_DIGITAL_BASE+0x81)
#define WCD939X_LB_IN_SEL_CTL (WCD939X_DIGITAL_BASE+0x82)
#define WCD939X_LOOP_BACK_MODE (WCD939X_DIGITAL_BASE+0x83)
#define WCD939X_SWR_DAC_TEST (WCD939X_DIGITAL_BASE+0x84)
#define WCD939X_SWR_HM_TEST_RX_0 (WCD939X_DIGITAL_BASE+0x85)
#define WCD939X_SWR_HM_TEST_TX_0 (WCD939X_DIGITAL_BASE+0x86)
#define WCD939X_SWR_HM_TEST_RX_1 (WCD939X_DIGITAL_BASE+0x87)
#define WCD939X_SWR_HM_TEST_TX_1 (WCD939X_DIGITAL_BASE+0x88)
#define WCD939X_SWR_HM_TEST_TX_2 (WCD939X_DIGITAL_BASE+0x89)
#define WCD939X_SWR_HM_TEST_0 (WCD939X_DIGITAL_BASE+0x8a)
#define WCD939X_SWR_HM_TEST_1 (WCD939X_DIGITAL_BASE+0x8b)
#define WCD939X_PAD_CTL_SWR_0 (WCD939X_DIGITAL_BASE+0x8c)
#define WCD939X_PAD_CTL_SWR_1 (WCD939X_DIGITAL_BASE+0x8d)
#define WCD939X_I2C_CTL (WCD939X_DIGITAL_BASE+0x8e)
#define WCD939X_CDC_TX_TANGGU_SW_MODE (WCD939X_DIGITAL_BASE+0x8f)
#define WCD939X_EFUSE_TEST_CTL_0 (WCD939X_DIGITAL_BASE+0x90)
#define WCD939X_EFUSE_TEST_CTL_1 (WCD939X_DIGITAL_BASE+0x91)
#define WCD939X_EFUSE_T_DATA_0 (WCD939X_DIGITAL_BASE+0x92)
#define WCD939X_EFUSE_T_DATA_1 (WCD939X_DIGITAL_BASE+0x93)
#define WCD939X_PAD_CTL_PDM_RX0 (WCD939X_DIGITAL_BASE+0x94)
#define WCD939X_PAD_CTL_PDM_RX1 (WCD939X_DIGITAL_BASE+0x95)
#define WCD939X_PAD_CTL_PDM_TX0 (WCD939X_DIGITAL_BASE+0x96)
#define WCD939X_PAD_CTL_PDM_TX1 (WCD939X_DIGITAL_BASE+0x97)
#define WCD939X_PAD_CTL_PDM_TX2 (WCD939X_DIGITAL_BASE+0x98)
#define WCD939X_PAD_INP_DIS_0 (WCD939X_DIGITAL_BASE+0x99)
#define WCD939X_PAD_INP_DIS_1 (WCD939X_DIGITAL_BASE+0x9a)
#define WCD939X_DRIVE_STRENGTH_0 (WCD939X_DIGITAL_BASE+0x9b)
#define WCD939X_DRIVE_STRENGTH_1 (WCD939X_DIGITAL_BASE+0x9c)
#define WCD939X_DRIVE_STRENGTH_2 (WCD939X_DIGITAL_BASE+0x9d)
#define WCD939X_RX_DATA_EDGE_CTL (WCD939X_DIGITAL_BASE+0x9e)
#define WCD939X_TX_DATA_EDGE_CTL (WCD939X_DIGITAL_BASE+0x9f)
#define WCD939X_GPIO_MODE (WCD939X_DIGITAL_BASE+0xa0)
#define WCD939X_PIN_CTL_OE (WCD939X_DIGITAL_BASE+0xa1)
#define WCD939X_PIN_CTL_DATA_0 (WCD939X_DIGITAL_BASE+0xa2)
#define WCD939X_PIN_CTL_DATA_1 (WCD939X_DIGITAL_BASE+0xa3)
#define WCD939X_PIN_STATUS_0 (WCD939X_DIGITAL_BASE+0xa4)
#define WCD939X_PIN_STATUS_1 (WCD939X_DIGITAL_BASE+0xa5)
#define WCD939X_DIG_DEBUG_CTL (WCD939X_DIGITAL_BASE+0xa6)
#define WCD939X_DIG_DEBUG_EN (WCD939X_DIGITAL_BASE+0xa7)
#define WCD939X_ANA_CSR_DBG_ADD (WCD939X_DIGITAL_BASE+0xa8)
#define WCD939X_ANA_CSR_DBG_CTL (WCD939X_DIGITAL_BASE+0xa9)
#define WCD939X_SSP_DBG (WCD939X_DIGITAL_BASE+0xaa)
#define WCD939X_MODE_STATUS_0 (WCD939X_DIGITAL_BASE+0xab)
#define WCD939X_MODE_STATUS_1 (WCD939X_DIGITAL_BASE+0xac)
#define WCD939X_SPARE_0 (WCD939X_DIGITAL_BASE+0xad)
#define WCD939X_SPARE_1 (WCD939X_DIGITAL_BASE+0xae)
#define WCD939X_SPARE_2 (WCD939X_DIGITAL_BASE+0xaf)
#define WCD939X_EFUSE_REG_0 (WCD939X_DIGITAL_BASE+0xb0)
#define WCD939X_EFUSE_REG_1 (WCD939X_DIGITAL_BASE+0xb1)
#define WCD939X_EFUSE_REG_2 (WCD939X_DIGITAL_BASE+0xb2)
#define WCD939X_EFUSE_REG_3 (WCD939X_DIGITAL_BASE+0xb3)
#define WCD939X_EFUSE_REG_4 (WCD939X_DIGITAL_BASE+0xb4)
#define WCD939X_EFUSE_REG_5 (WCD939X_DIGITAL_BASE+0xb5)
#define WCD939X_EFUSE_REG_6 (WCD939X_DIGITAL_BASE+0xb6)
#define WCD939X_EFUSE_REG_7 (WCD939X_DIGITAL_BASE+0xb7)
#define WCD939X_EFUSE_REG_8 (WCD939X_DIGITAL_BASE+0xb8)
#define WCD939X_EFUSE_REG_9 (WCD939X_DIGITAL_BASE+0xb9)
#define WCD939X_EFUSE_REG_10 (WCD939X_DIGITAL_BASE+0xba)
#define WCD939X_EFUSE_REG_11 (WCD939X_DIGITAL_BASE+0xbb)
#define WCD939X_EFUSE_REG_12 (WCD939X_DIGITAL_BASE+0xbc)
#define WCD939X_EFUSE_REG_13 (WCD939X_DIGITAL_BASE+0xbd)
#define WCD939X_EFUSE_REG_14 (WCD939X_DIGITAL_BASE+0xbe)
#define WCD939X_EFUSE_REG_15 (WCD939X_DIGITAL_BASE+0xbf)
#define WCD939X_EFUSE_REG_16 (WCD939X_DIGITAL_BASE+0xc0)
#define WCD939X_EFUSE_REG_17 (WCD939X_DIGITAL_BASE+0xc1)
#define WCD939X_EFUSE_REG_18 (WCD939X_DIGITAL_BASE+0xc2)
#define WCD939X_EFUSE_REG_19 (WCD939X_DIGITAL_BASE+0xc3)
#define WCD939X_EFUSE_REG_20 (WCD939X_DIGITAL_BASE+0xc4)
#define WCD939X_EFUSE_REG_21 (WCD939X_DIGITAL_BASE+0xc5)
#define WCD939X_EFUSE_REG_22 (WCD939X_DIGITAL_BASE+0xc6)
#define WCD939X_EFUSE_REG_23 (WCD939X_DIGITAL_BASE+0xc7)
#define WCD939X_EFUSE_REG_24 (WCD939X_DIGITAL_BASE+0xc8)
#define WCD939X_EFUSE_REG_25 (WCD939X_DIGITAL_BASE+0xc9)
#define WCD939X_EFUSE_REG_26 (WCD939X_DIGITAL_BASE+0xca)
#define WCD939X_EFUSE_REG_27 (WCD939X_DIGITAL_BASE+0xcb)
#define WCD939X_EFUSE_REG_28 (WCD939X_DIGITAL_BASE+0xcc)
#define WCD939X_EFUSE_REG_29 (WCD939X_DIGITAL_BASE+0xcd)
#define WCD939X_EFUSE_REG_30 (WCD939X_DIGITAL_BASE+0xce)
#define WCD939X_EFUSE_REG_31 (WCD939X_DIGITAL_BASE+0xcf)
#define WCD939X_TX_REQ_FB_CTL_0 (WCD939X_DIGITAL_BASE+0xd0)
#define WCD939X_TX_REQ_FB_CTL_1 (WCD939X_DIGITAL_BASE+0xd1)
#define WCD939X_TX_REQ_FB_CTL_2 (WCD939X_DIGITAL_BASE+0xd2)
#define WCD939X_TX_REQ_FB_CTL_3 (WCD939X_DIGITAL_BASE+0xd3)
#define WCD939X_TX_REQ_FB_CTL_4 (WCD939X_DIGITAL_BASE+0xd4)
#define WCD939X_DEM_BYPASS_DATA0 (WCD939X_DIGITAL_BASE+0xd5)
#define WCD939X_DEM_BYPASS_DATA1 (WCD939X_DIGITAL_BASE+0xd6)
#define WCD939X_DEM_BYPASS_DATA2 (WCD939X_DIGITAL_BASE+0xd7)
#define WCD939X_DEM_BYPASS_DATA3 (WCD939X_DIGITAL_BASE+0xd8)
#define WCD939X_DEM_SECOND_ORDER (WCD939X_DIGITAL_BASE+0xd9)
#define WCD939X_DSM_CTRL (WCD939X_DIGITAL_BASE+0xda)
#define WCD939X_DSM_0_STATIC_DATA_0 (WCD939X_DIGITAL_BASE+0xdb)
#define WCD939X_DSM_0_STATIC_DATA_1 (WCD939X_DIGITAL_BASE+0xdc)
#define WCD939X_DSM_0_STATIC_DATA_2 (WCD939X_DIGITAL_BASE+0xdd)
#define WCD939X_DSM_0_STATIC_DATA_3 (WCD939X_DIGITAL_BASE+0xde)
#define WCD939X_DSM_1_STATIC_DATA_0 (WCD939X_DIGITAL_BASE+0xdf)
#define WCD939X_DSM_1_STATIC_DATA_1 (WCD939X_DIGITAL_BASE+0xe0)
#define WCD939X_DSM_1_STATIC_DATA_2 (WCD939X_DIGITAL_BASE+0xe1)
#define WCD939X_DSM_1_STATIC_DATA_3 (WCD939X_DIGITAL_BASE+0xe2)
#define WCD939X_RX_PAGE (WCD939X_RX_BASE+0x00)
#define WCD939X_TOP_CFG0 (WCD939X_RX_BASE+0x01)
#define WCD939X_HPHL_COMP_WR_LSB (WCD939X_RX_BASE+0x02)
#define WCD939X_HPHL_COMP_WR_MSB (WCD939X_RX_BASE+0x03)
#define WCD939X_HPHL_COMP_LUT (WCD939X_RX_BASE+0x04)
#define WCD939X_HPHL_COMP_RD_LSB (WCD939X_RX_BASE+0x05)
#define WCD939X_HPHL_COMP_RD_MSB (WCD939X_RX_BASE+0x06)
#define WCD939X_HPHR_COMP_WR_LSB (WCD939X_RX_BASE+0x07)
#define WCD939X_HPHR_COMP_WR_MSB (WCD939X_RX_BASE+0x08)
#define WCD939X_HPHR_COMP_LUT (WCD939X_RX_BASE+0x09)
#define WCD939X_HPHR_COMP_RD_LSB (WCD939X_RX_BASE+0x0a)
#define WCD939X_HPHR_COMP_RD_MSB (WCD939X_RX_BASE+0x0b)
#define WCD939X_DSD0_DEBUG_CFG1 (WCD939X_RX_BASE+0x0c)
#define WCD939X_DSD0_DEBUG_CFG2 (WCD939X_RX_BASE+0x0d)
#define WCD939X_DSD0_DEBUG_CFG3 (WCD939X_RX_BASE+0x0e)
#define WCD939X_DSD0_DEBUG_CFG4 (WCD939X_RX_BASE+0x0f)
#define WCD939X_DSD0_DEBUG_CFG5 (WCD939X_RX_BASE+0x10)
#define WCD939X_DSD0_DEBUG_CFG6 (WCD939X_RX_BASE+0x11)
#define WCD939X_DSD1_DEBUG_CFG1 (WCD939X_RX_BASE+0x12)
#define WCD939X_DSD1_DEBUG_CFG2 (WCD939X_RX_BASE+0x13)
#define WCD939X_DSD1_DEBUG_CFG3 (WCD939X_RX_BASE+0x14)
#define WCD939X_DSD1_DEBUG_CFG4 (WCD939X_RX_BASE+0x15)
#define WCD939X_DSD1_DEBUG_CFG5 (WCD939X_RX_BASE+0x16)
#define WCD939X_DSD1_DEBUG_CFG6 (WCD939X_RX_BASE+0x17)
#define WCD939X_HPHL_RX_PATH_CFG0 (WCD939X_RX_BASE+0x1c)
#define WCD939X_HPHL_RX_PATH_CFG1 (WCD939X_RX_BASE+0x1d)
#define WCD939X_HPHR_RX_PATH_CFG0 (WCD939X_RX_BASE+0x1e)
#define WCD939X_HPHR_RX_PATH_CFG1 (WCD939X_RX_BASE+0x1f)
#define WCD939X_RX_PATH_CFG2 (WCD939X_RX_BASE+0x20)
#define WCD939X_HPHL_RX_PATH_SEC0 (WCD939X_RX_BASE+0x21)
#define WCD939X_HPHL_RX_PATH_SEC1 (WCD939X_RX_BASE+0x22)
#define WCD939X_HPHL_RX_PATH_SEC2 (WCD939X_RX_BASE+0x23)
#define WCD939X_HPHL_RX_PATH_SEC3 (WCD939X_RX_BASE+0x24)
#define WCD939X_HPHR_RX_PATH_SEC0 (WCD939X_RX_BASE+0x25)
#define WCD939X_HPHR_RX_PATH_SEC1 (WCD939X_RX_BASE+0x26)
#define WCD939X_HPHR_RX_PATH_SEC2 (WCD939X_RX_BASE+0x27)
#define WCD939X_HPHR_RX_PATH_SEC3 (WCD939X_RX_BASE+0x28)
#define WCD939X_RX_PATH_SEC4 (WCD939X_RX_BASE+0x29)
#define WCD939X_RX_PATH_SEC5 (WCD939X_RX_BASE+0x2a)
#define WCD939X_COMPANDER_HPHL_BASE (WCD939X_BASE+0x541)
#define WCD939X_CTL0 (WCD939X_COMPANDER_HPHL_BASE+0x00)
#define WCD939X_CTL1 (WCD939X_COMPANDER_HPHL_BASE+0x01)
#define WCD939X_CTL2 (WCD939X_COMPANDER_HPHL_BASE+0x02)
#define WCD939X_CTL3 (WCD939X_COMPANDER_HPHL_BASE+0x03)
#define WCD939X_CTL4 (WCD939X_COMPANDER_HPHL_BASE+0x04)
#define WCD939X_CTL5 (WCD939X_COMPANDER_HPHL_BASE+0x05)
#define WCD939X_CTL6 (WCD939X_COMPANDER_HPHL_BASE+0x06)
#define WCD939X_CTL7 (WCD939X_COMPANDER_HPHL_BASE+0x07)
#define WCD939X_CTL8 (WCD939X_COMPANDER_HPHL_BASE+0x08)
#define WCD939X_CTL9 (WCD939X_COMPANDER_HPHL_BASE+0x09)
#define WCD939X_CTL10 (WCD939X_COMPANDER_HPHL_BASE+0x0a)
#define WCD939X_CTL11 (WCD939X_COMPANDER_HPHL_BASE+0x0b)
#define WCD939X_CTL12 (WCD939X_COMPANDER_HPHL_BASE+0x0c)
#define WCD939X_CTL13 (WCD939X_COMPANDER_HPHL_BASE+0x0d)
#define WCD939X_CTL14 (WCD939X_COMPANDER_HPHL_BASE+0x0e)
#define WCD939X_CTL15 (WCD939X_COMPANDER_HPHL_BASE+0x0f)
#define WCD939X_CTL16 (WCD939X_COMPANDER_HPHL_BASE+0x10)
#define WCD939X_CTL17 (WCD939X_COMPANDER_HPHL_BASE+0x11)
#define WCD939X_CTL18 (WCD939X_COMPANDER_HPHL_BASE+0x12)
#define WCD939X_CTL19 (WCD939X_COMPANDER_HPHL_BASE+0x13)
#define WCD939X_R_BASE (WCD939X_BASE+0x561)
#define WCD939X_R_CTL0 (WCD939X_R_BASE+0x00)
#define WCD939X_R_CTL1 (WCD939X_R_BASE+0x01)
#define WCD939X_R_CTL2 (WCD939X_R_BASE+0x02)
#define WCD939X_R_CTL3 (WCD939X_R_BASE+0x03)
#define WCD939X_R_CTL4 (WCD939X_R_BASE+0x04)
#define WCD939X_R_CTL5 (WCD939X_R_BASE+0x05)
#define WCD939X_R_CTL6 (WCD939X_R_BASE+0x06)
#define WCD939X_R_CTL7 (WCD939X_R_BASE+0x07)
#define WCD939X_R_CTL8 (WCD939X_R_BASE+0x08)
#define WCD939X_R_CTL9 (WCD939X_R_BASE+0x09)
#define WCD939X_R_CTL10 (WCD939X_R_BASE+0x0a)
#define WCD939X_R_CTL11 (WCD939X_R_BASE+0x0b)
#define WCD939X_R_CTL12 (WCD939X_R_BASE+0x0c)
#define WCD939X_R_CTL13 (WCD939X_R_BASE+0x0d)
#define WCD939X_R_CTL14 (WCD939X_R_BASE+0x0e)
#define WCD939X_R_CTL15 (WCD939X_R_BASE+0x0f)
#define WCD939X_R_CTL16 (WCD939X_R_BASE+0x10)
#define WCD939X_R_CTL17 (WCD939X_R_BASE+0x11)
#define WCD939X_R_CTL18 (WCD939X_R_BASE+0x12)
#define WCD939X_R_CTL19 (WCD939X_R_BASE+0x13)
#define WCD939X_E_BASE (WCD939X_BASE+0x581)
#define WCD939X_PATH_CTL (WCD939X_E_BASE+0x00)
#define WCD939X_CFG0 (WCD939X_E_BASE+0x01)
#define WCD939X_CFG1 (WCD939X_E_BASE+0x02)
#define WCD939X_CFG2 (WCD939X_E_BASE+0x03)
#define WCD939X_CFG3 (WCD939X_E_BASE+0x04)
#define WCD939X_DSD_HPHL_BASE (WCD939X_BASE+0x591)
#define WCD939X_DSD_HPHL_PATH_CTL (WCD939X_DSD_HPHL_BASE+0x00)
#define WCD939X_DSD_HPHL_CFG0 (WCD939X_DSD_HPHL_BASE+0x01)
#define WCD939X_DSD_HPHL_CFG1 (WCD939X_DSD_HPHL_BASE+0x02)
#define WCD939X_DSD_HPHL_CFG2 (WCD939X_DSD_HPHL_BASE+0x03)
#define WCD939X_DSD_HPHL_CFG3 (WCD939X_DSD_HPHL_BASE+0x04)
#define WCD939X_CFG4 (WCD939X_DSD_HPHL_BASE+0x05)
#define WCD939X_CFG5 (WCD939X_DSD_HPHL_BASE+0x06)
#define WCD939X_DSD_HPHR_BASE (WCD939X_BASE+0x5a1)
#define WCD939X_DSD_HPHR_PATH_CTL (WCD939X_DSD_HPHR_BASE+0x00)
#define WCD939X_DSD_HPHR_CFG0 (WCD939X_DSD_HPHR_BASE+0x01)
#define WCD939X_DSD_HPHR_CFG1 (WCD939X_DSD_HPHR_BASE+0x02)
#define WCD939X_DSD_HPHR_CFG2 (WCD939X_DSD_HPHR_BASE+0x03)
#define WCD939X_DSD_HPHR_CFG3 (WCD939X_DSD_HPHR_BASE+0x04)
#define WCD939X_DSD_HPHR_CFG4 (WCD939X_DSD_HPHR_BASE+0x05)
#define WCD939X_DSD_HPHR_CFG5 (WCD939X_DSD_HPHR_BASE+0x06)
#define WCD939X_NUM_REGISTERS (WCD939X_DSD_HPHR_CFG5+1)
#define WCD939X_MAX_REGISTER (WCD939X_NUM_REGISTERS-1)
#endif /* WCD939X_REGISTERS_H */

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asoc/codecs/wcd939x/wcd939x-regmap.c Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2018-2019, 2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/regmap.h>
#include <linux/device.h>
#include "wcd939x-registers.h"
extern const u8 wcd939x_reg_access[WCD939X_NUM_REGISTERS];
static struct reg_default wcd939x_defaults[] = {
{WCD939X_ANA_PAGE, 0x00},
{WCD939X_BIAS, 0x00},
{WCD939X_RX_SUPPLIES, 0x00},
{WCD939X_HPH, 0x0c},
{WCD939X_EAR, 0x00},
{WCD939X_EAR_COMPANDER_CTL, 0x02},
{WCD939X_TX_CH1, 0x20},
{WCD939X_TX_CH2, 0x00},
{WCD939X_TX_CH3, 0x20},
{WCD939X_TX_CH4, 0x00},
{WCD939X_MICB1_MICB2_DSP_EN_LOGIC, 0x00},
{WCD939X_MICB3_DSP_EN_LOGIC, 0x00},
{WCD939X_MBHC_MECH, 0x39},
{WCD939X_MBHC_ELECT, 0x08},
{WCD939X_MBHC_ZDET, 0x00},
{WCD939X_MBHC_RESULT_1, 0x00},
{WCD939X_MBHC_RESULT_2, 0x00},
{WCD939X_MBHC_RESULT_3, 0x00},
{WCD939X_MBHC_BTN0, 0x00},
{WCD939X_MBHC_BTN1, 0x10},
{WCD939X_MBHC_BTN2, 0x20},
{WCD939X_MBHC_BTN3, 0x30},
{WCD939X_MBHC_BTN4, 0x40},
{WCD939X_MBHC_BTN5, 0x50},
{WCD939X_MBHC_BTN6, 0x60},
{WCD939X_MBHC_BTN7, 0x70},
{WCD939X_MICB1, 0x10},
{WCD939X_MICB2, 0x10},
{WCD939X_MICB2_RAMP, 0x00},
{WCD939X_MICB3, 0x00},
{WCD939X_MICB4, 0x00},
{WCD939X_CTL, 0x2a},
{WCD939X_VBG_FINE_ADJ, 0x55},
{WCD939X_VDDCX_ADJUST, 0x01},
{WCD939X_DISABLE_LDOL, 0x00},
{WCD939X_CTL_CLK, 0x00},
{WCD939X_CTL_ANA, 0x00},
{WCD939X_ZDET_VNEG_CTL, 0x00},
{WCD939X_ZDET_BIAS_CTL, 0x46},
{WCD939X_CTL_BCS, 0x00},
{WCD939X_MOISTURE_DET_FSM_STATUS, 0x00},
{WCD939X_TEST_CTL, 0x00},
{WCD939X_MODE, 0x2b},
{WCD939X_LDOH_BIAS, 0x68},
{WCD939X_STB_LOADS, 0x00},
{WCD939X_SLOWRAMP, 0x50},
{WCD939X_TEST_CTL_1, 0x1a},
{WCD939X_TEST_CTL_2, 0x00},
{WCD939X_TEST_CTL_3, 0xa4},
{WCD939X_MICB2_TEST_CTL_1, 0x1a},
{WCD939X_MICB2_TEST_CTL_2, 0x00},
{WCD939X_MICB2_TEST_CTL_3, 0x24},
{WCD939X_MICB3_TEST_CTL_1, 0x1a},
{WCD939X_MICB3_TEST_CTL_2, 0x00},
{WCD939X_MICB3_TEST_CTL_3, 0xa4},
{WCD939X_MICB4_TEST_CTL_1, 0x1a},
{WCD939X_MICB4_TEST_CTL_2, 0x00},
{WCD939X_MICB4_TEST_CTL_3, 0xa4},
{WCD939X_ADC_VCM, 0x39},
{WCD939X_BIAS_ATEST, 0xe0},
{WCD939X_SPARE1, 0x00},
{WCD939X_SPARE2, 0x00},
{WCD939X_TXFE_DIV_CTL, 0x22},
{WCD939X_TXFE_DIV_START, 0x00},
{WCD939X_SPARE3, 0x00},
{WCD939X_SPARE4, 0x00},
{WCD939X_TEST_EN, 0xcc},
{WCD939X_ADC_IB, 0xe9},
{WCD939X_ATEST_REFCTL, 0x0b},
{WCD939X_TX_1_2_TEST_CTL, 0x38},
{WCD939X_TEST_BLK_EN1, 0xff},
{WCD939X_TXFE1_CLKDIV, 0x00},
{WCD939X_SAR2_ERR, 0x00},
{WCD939X_SAR1_ERR, 0x00},
{WCD939X_TX_3_4_TEST_EN, 0xcc},
{WCD939X_TX_3_4_ADC_IB, 0xe9},
{WCD939X_TX_3_4_ATEST_REFCTL, 0x0b},
{WCD939X_TX_3_4_TEST_CTL, 0x38},
{WCD939X_TEST_BLK_EN3, 0xff},
{WCD939X_TXFE3_CLKDIV, 0x00},
{WCD939X_SAR4_ERR, 0x00},
{WCD939X_SAR3_ERR, 0x00},
{WCD939X_TEST_BLK_EN2, 0xfb},
{WCD939X_TXFE2_CLKDIV, 0x00},
{WCD939X_TX_3_4_SPARE1, 0x00},
{WCD939X_TEST_BLK_EN4, 0xfb},
{WCD939X_TXFE4_CLKDIV, 0x00},
{WCD939X_TX_3_4_SPARE2, 0x00},
{WCD939X_MODE_1, 0x40},
{WCD939X_MODE_2, 0x3a},
{WCD939X_MODE_3, 0xf0},
{WCD939X_CTRL_VCL_1, 0x7c},
{WCD939X_CTRL_VCL_2, 0x82},
{WCD939X_CTRL_CCL_1, 0x31},
{WCD939X_CTRL_CCL_2, 0x80},
{WCD939X_CTRL_CCL_3, 0x80},
{WCD939X_CTRL_CCL_4, 0x51},
{WCD939X_CTRL_CCL_5, 0x00},
{WCD939X_BUCK_TMUX_A_D, 0x00},
{WCD939X_BUCK_SW_DRV_CNTL, 0x77},
{WCD939X_SPARE, 0x80},
{WCD939X_EN, 0x4e},
{WCD939X_VNEG_CTRL_1, 0x0b},
{WCD939X_VNEG_CTRL_2, 0x45},
{WCD939X_VNEG_CTRL_3, 0x14},
{WCD939X_VNEG_CTRL_4, 0xdb},
{WCD939X_VNEG_CTRL_5, 0x83},
{WCD939X_VNEG_CTRL_6, 0x98},
{WCD939X_VNEG_CTRL_7, 0xa9},
{WCD939X_VNEG_CTRL_8, 0x68},
{WCD939X_VNEG_CTRL_9, 0x66},
{WCD939X_VNEGDAC_CTRL_1, 0xed},
{WCD939X_VNEGDAC_CTRL_2, 0xf8},
{WCD939X_VNEGDAC_CTRL_3, 0xa6},
{WCD939X_CTRL_1, 0x65},
{WCD939X_FLYBACK_TEST_CTL, 0x02},
{WCD939X_AUX_SW_CTL, 0x00},
{WCD939X_PA_AUX_IN_CONN, 0x01},
{WCD939X_TIMER_DIV, 0x32},
{WCD939X_OCP_CTL, 0x1f},
{WCD939X_OCP_COUNT, 0x77},
{WCD939X_BIAS_EAR_DAC, 0xa0},
{WCD939X_BIAS_EAR_AMP, 0xaa},
{WCD939X_BIAS_HPH_LDO, 0xa9},
{WCD939X_BIAS_HPH_PA, 0xaa},
{WCD939X_BIAS_HPH_RDACBUFF_CNP2, 0xca},
{WCD939X_BIAS_HPH_RDAC_LDO, 0x88},
{WCD939X_BIAS_HPH_CNP1, 0x82},
{WCD939X_BIAS_HPH_LOWPOWER, 0x82},
{WCD939X_BIAS_AUX_DAC, 0xa0},
{WCD939X_BIAS_AUX_AMP, 0xaa},
{WCD939X_BIAS_VNEGDAC_BLEEDER, 0x50},
{WCD939X_BIAS_MISC, 0x00},
{WCD939X_BIAS_BUCK_RST, 0x08},
{WCD939X_BIAS_BUCK_VREF_ERRAMP, 0x44},
{WCD939X_BIAS_FLYB_ERRAMP, 0x40},
{WCD939X_BIAS_FLYB_BUFF, 0xaa},
{WCD939X_BIAS_FLYB_MID_RST, 0x14},
{WCD939X_L_STATUS, 0x04},
{WCD939X_R_STATUS, 0x04},
{WCD939X_CNP_EN, 0x80},
{WCD939X_CNP_WG_CTL, 0x9a},
{WCD939X_CNP_WG_TIME, 0x14},
{WCD939X_HPH_OCP_CTL, 0x28},
{WCD939X_AUTO_CHOP, 0x56},
{WCD939X_CHOP_CTL, 0x83},
{WCD939X_PA_CTL1, 0x46},
{WCD939X_PA_CTL2, 0x50},
{WCD939X_L_EN, 0x80},
{WCD939X_L_TEST, 0xe0},
{WCD939X_L_ATEST, 0x50},
{WCD939X_R_EN, 0x80},
{WCD939X_R_TEST, 0xe0},
{WCD939X_R_ATEST, 0x50},
{WCD939X_RDAC_CLK_CTL1, 0x80},
{WCD939X_RDAC_CLK_CTL2, 0x0b},
{WCD939X_RDAC_LDO_CTL, 0x33},
{WCD939X_RDAC_CHOP_CLK_LP_CTL, 0x00},
{WCD939X_REFBUFF_UHQA_CTL, 0x00},
{WCD939X_REFBUFF_LP_CTL, 0x8e},
{WCD939X_L_DAC_CTL, 0x20},
{WCD939X_R_DAC_CTL, 0x20},
{WCD939X_HPHLR_SURGE_COMP_SEL, 0x55},
{WCD939X_HPHLR_SURGE_EN, 0x19},
{WCD939X_HPHLR_SURGE_MISC1, 0xa0},
{WCD939X_HPHLR_SURGE_STATUS, 0x00},
{WCD939X_EAR_EN_REG, 0x22},
{WCD939X_EAR_PA_CON, 0x44},
{WCD939X_EAR_SP_CON, 0xdb},
{WCD939X_EAR_DAC_CON, 0x80},
{WCD939X_EAR_CNP_FSM_CON, 0xb2},
{WCD939X_EAR_TEST_CTL, 0x00},
{WCD939X_STATUS_REG_1, 0x00},
{WCD939X_STATUS_REG_2, 0x08},
{WCD939X_ANA_NEW_PAGE, 0x00},
{WCD939X_ANA_HPH2, 0x00},
{WCD939X_ANA_HPH3, 0x00},
{WCD939X_SLEEP_CTL, 0x18},
{WCD939X_WATCHDOG_CTL, 0x00},
{WCD939X_ELECT_REM_CLAMP_CTL, 0x00},
{WCD939X_CTL_1, 0x02},
{WCD939X_CTL_2, 0x05},
{WCD939X_PLUG_DETECT_CTL, 0xe9},
{WCD939X_ZDET_ANA_CTL, 0x0f},
{WCD939X_ZDET_RAMP_CTL, 0x00},
{WCD939X_FSM_STATUS, 0x00},
{WCD939X_ADC_RESULT, 0x00},
{WCD939X_TX_CH12_MUX, 0x11},
{WCD939X_TX_CH34_MUX, 0x23},
{WCD939X_DIE_CRK_DET_EN, 0x00},
{WCD939X_DIE_CRK_DET_OUT, 0x00},
{WCD939X_RDAC_GAIN_CTL, 0x00},
{WCD939X_PA_GAIN_CTL_L, 0x00},
{WCD939X_RDAC_VREF_CTL, 0x08},
{WCD939X_RDAC_OVERRIDE_CTL, 0x00},
{WCD939X_PA_GAIN_CTL_R, 0x00},
{WCD939X_PA_MISC1, 0x32},
{WCD939X_PA_MISC2, 0x00},
{WCD939X_PA_RDAC_MISC, 0x00},
{WCD939X_HPH_TIMER1, 0xfe},
{WCD939X_HPH_TIMER2, 0x02},
{WCD939X_HPH_TIMER3, 0x4e},
{WCD939X_HPH_TIMER4, 0x54},
{WCD939X_PA_RDAC_MISC2, 0x0b},
{WCD939X_PA_RDAC_MISC3, 0x00},
{WCD939X_RDAC_HD2_CTL_L, 0xa0},
{WCD939X_RDAC_HD2_CTL_R, 0xa0},
{WCD939X_HPH_RDAC_BIAS_LOHIFI, 0x64},
{WCD939X_HPH_RDAC_BIAS_ULP, 0x01},
{WCD939X_HPH_RDAC_LDO_LP, 0x11},
{WCD939X_MOISTURE_DET_DC_CTRL, 0x57},
{WCD939X_MOISTURE_DET_POLLING_CTRL, 0x01},
{WCD939X_MECH_DET_CURRENT, 0x00},
{WCD939X_ZDET_CLK_AND_MOISTURE_CTL_NEW, 0x47},
{WCD939X_EAR_CHOPPER_CON, 0xa8},
{WCD939X_CNP_VCM_CON1, 0x42},
{WCD939X_CNP_VCM_CON2, 0x22},
{WCD939X_EAR_DYNAMIC_BIAS, 0x00},
{WCD939X_WATCHDOG_CTL_1, 0x0a},
{WCD939X_WATCHDOG_CTL_2, 0x0a},
{WCD939X_DIE_CRK_DET_INT1, 0x02},
{WCD939X_DIE_CRK_DET_INT2, 0x60},
{WCD939X_TXFE_DIVSTOP_L2, 0xff},
{WCD939X_TXFE_DIVSTOP_L1, 0x7f},
{WCD939X_TXFE_DIVSTOP_L0, 0x3f},
{WCD939X_TXFE_DIVSTOP_ULP1P2M, 0x1f},
{WCD939X_TXFE_DIVSTOP_ULP0P6M, 0x0f},
{WCD939X_TXFE_ICTRL_STG1_L2L1, 0xd7},
{WCD939X_TXFE_ICTRL_STG1_L0, 0xc8},
{WCD939X_TXFE_ICTRL_STG1_ULP, 0xc6},
{WCD939X_TXFE_ICTRL_STG2MAIN_L2L1, 0x95},
{WCD939X_TXFE_ICTRL_STG2MAIN_L0, 0x6a},
{WCD939X_TXFE_ICTRL_STG2MAIN_ULP, 0x05},
{WCD939X_TXFE_ICTRL_STG2CASC_L2L1L0, 0xa5},
{WCD939X_TXFE_ICTRL_STG2CASC_ULP, 0x13},
{WCD939X_TXADC_SCBIAS_L2L1, 0x88},
{WCD939X_TXADC_SCBIAS_L0ULP, 0x42},
{WCD939X_TXADC_INT_L2, 0xff},
{WCD939X_TXADC_INT_L1, 0x64},
{WCD939X_TXADC_INT_L0, 0x64},
{WCD939X_TXADC_INT_ULP, 0x77},
{WCD939X_DIGITAL_PAGE, 0x00},
{WCD939X_CHIP_ID0, 0x00},
{WCD939X_CHIP_ID1, 0x00},
{WCD939X_CHIP_ID2, 0x0e},
{WCD939X_CHIP_ID3, 0x01},
{WCD939X_SWR_TX_CLK_RATE, 0x00},
{WCD939X_CDC_RST_CTL, 0x03},
{WCD939X_TOP_CLK_CFG, 0x00},
{WCD939X_CDC_ANA_CLK_CTL, 0x00},
{WCD939X_CDC_DIG_CLK_CTL, 0xf0},
{WCD939X_SWR_RST_EN, 0x00},
{WCD939X_CDC_PATH_MODE, 0x55},
{WCD939X_CDC_RX_RST, 0x00},
{WCD939X_CDC_RX0_CTL, 0xfc},
{WCD939X_CDC_RX1_CTL, 0xfc},
{WCD939X_CDC_RX2_CTL, 0xfc},
{WCD939X_CDC_TX_ANA_MODE_0_1, 0x00},
{WCD939X_CDC_TX_ANA_MODE_2_3, 0x00},
{WCD939X_CDC_COMP_CTL_0, 0x00},
{WCD939X_CDC_ANA_TX_CLK_CTL, 0x1e},
{WCD939X_CDC_HPH_DSM_A1_0, 0x00},
{WCD939X_CDC_HPH_DSM_A1_1, 0x01},
{WCD939X_CDC_HPH_DSM_A2_0, 0x63},
{WCD939X_CDC_HPH_DSM_A2_1, 0x04},
{WCD939X_CDC_HPH_DSM_A3_0, 0xac},
{WCD939X_CDC_HPH_DSM_A3_1, 0x04},
{WCD939X_CDC_HPH_DSM_A4_0, 0x1a},
{WCD939X_CDC_HPH_DSM_A4_1, 0x03},
{WCD939X_CDC_HPH_DSM_A5_0, 0xbc},
{WCD939X_CDC_HPH_DSM_A5_1, 0x02},
{WCD939X_CDC_HPH_DSM_A6_0, 0xc7},
{WCD939X_CDC_HPH_DSM_A7_0, 0xf8},
{WCD939X_CDC_HPH_DSM_C_0, 0x47},
{WCD939X_CDC_HPH_DSM_C_1, 0x43},
{WCD939X_CDC_HPH_DSM_C_2, 0xb1},
{WCD939X_CDC_HPH_DSM_C_3, 0x17},
{WCD939X_CDC_HPH_DSM_R1, 0x4d},
{WCD939X_CDC_HPH_DSM_R2, 0x29},
{WCD939X_CDC_HPH_DSM_R3, 0x34},
{WCD939X_CDC_HPH_DSM_R4, 0x59},
{WCD939X_CDC_HPH_DSM_R5, 0x66},
{WCD939X_CDC_HPH_DSM_R6, 0x87},
{WCD939X_CDC_HPH_DSM_R7, 0x64},
{WCD939X_CDC_EAR_DSM_A1_0, 0x00},
{WCD939X_CDC_EAR_DSM_A1_1, 0x01},
{WCD939X_CDC_EAR_DSM_A2_0, 0x96},
{WCD939X_CDC_EAR_DSM_A2_1, 0x09},
{WCD939X_CDC_EAR_DSM_A3_0, 0xab},
{WCD939X_CDC_EAR_DSM_A3_1, 0x05},
{WCD939X_CDC_EAR_DSM_A4_0, 0x1c},
{WCD939X_CDC_EAR_DSM_A4_1, 0x02},
{WCD939X_CDC_EAR_DSM_A5_0, 0x17},
{WCD939X_CDC_EAR_DSM_A5_1, 0x02},
{WCD939X_CDC_EAR_DSM_A6_0, 0xaa},
{WCD939X_CDC_EAR_DSM_A7_0, 0xe3},
{WCD939X_CDC_EAR_DSM_C_0, 0x69},
{WCD939X_CDC_EAR_DSM_C_1, 0x54},
{WCD939X_CDC_EAR_DSM_C_2, 0x02},
{WCD939X_CDC_EAR_DSM_C_3, 0x15},
{WCD939X_CDC_EAR_DSM_R1, 0xa4},
{WCD939X_CDC_EAR_DSM_R2, 0xb5},
{WCD939X_CDC_EAR_DSM_R3, 0x86},
{WCD939X_CDC_EAR_DSM_R4, 0x85},
{WCD939X_CDC_EAR_DSM_R5, 0xaa},
{WCD939X_CDC_EAR_DSM_R6, 0xe2},
{WCD939X_CDC_EAR_DSM_R7, 0x62},
{WCD939X_CDC_HPH_GAIN_RX_0, 0x55},
{WCD939X_CDC_HPH_GAIN_RX_1, 0xa9},
{WCD939X_CDC_HPH_GAIN_DSD_0, 0x3d},
{WCD939X_CDC_HPH_GAIN_DSD_1, 0x2e},
{WCD939X_CDC_HPH_GAIN_DSD_2, 0x01},
{WCD939X_CDC_EAR_GAIN_DSD_0, 0x00},
{WCD939X_CDC_EAR_GAIN_DSD_1, 0xfc},
{WCD939X_CDC_EAR_GAIN_DSD_2, 0x01},
{WCD939X_CDC_HPH_GAIN_CTL, 0x00},
{WCD939X_CDC_EAR_GAIN_CTL, 0x00},
{WCD939X_CDC_EAR_PATH_CTL, 0x00},
{WCD939X_CDC_SWR_CLH, 0x00},
{WCD939X_SWR_CLH_BYP, 0x00},
{WCD939X_CDC_TX0_CTL, 0x68},
{WCD939X_CDC_TX1_CTL, 0x68},
{WCD939X_CDC_TX2_CTL, 0x68},
{WCD939X_CDC_TX_RST, 0x00},
{WCD939X_CDC_REQ_CTL, 0x01},
{WCD939X_CDC_RST, 0x00},
{WCD939X_CDC_AMIC_CTL, 0x0f},
{WCD939X_CDC_DMIC_CTL, 0x04},
{WCD939X_CDC_DMIC1_CTL, 0x01},
{WCD939X_CDC_DMIC2_CTL, 0x01},
{WCD939X_CDC_DMIC3_CTL, 0x01},
{WCD939X_CDC_DMIC4_CTL, 0x01},
{WCD939X_EFUSE_PRG_CTL, 0x00},
{WCD939X_EFUSE_CTL, 0x2b},
{WCD939X_CDC_DMIC_RATE_1_2, 0x11},
{WCD939X_CDC_DMIC_RATE_3_4, 0x11},
{WCD939X_PDM_WD_CTL0, 0x00},
{WCD939X_PDM_WD_CTL1, 0x00},
{WCD939X_PDM_WD_CTL2, 0x00},
{WCD939X_INTR_MODE, 0x00},
{WCD939X_INTR_MASK_0, 0xff},
{WCD939X_INTR_MASK_1, 0xe7},
{WCD939X_INTR_MASK_2, 0x0e},
{WCD939X_INTR_STATUS_0, 0x00},
{WCD939X_INTR_STATUS_1, 0x00},
{WCD939X_INTR_STATUS_2, 0x00},
{WCD939X_INTR_CLEAR_0, 0x00},
{WCD939X_INTR_CLEAR_1, 0x00},
{WCD939X_INTR_CLEAR_2, 0x00},
{WCD939X_INTR_LEVEL_0, 0x00},
{WCD939X_INTR_LEVEL_1, 0x00},
{WCD939X_INTR_LEVEL_2, 0x00},
{WCD939X_INTR_SET_0, 0x00},
{WCD939X_INTR_SET_1, 0x00},
{WCD939X_INTR_SET_2, 0x00},
{WCD939X_INTR_TEST_0, 0x00},
{WCD939X_INTR_TEST_1, 0x00},
{WCD939X_INTR_TEST_2, 0x00},
{WCD939X_TX_MODE_DBG_EN, 0x00},
{WCD939X_TX_MODE_DBG_0_1, 0x00},
{WCD939X_TX_MODE_DBG_2_3, 0x00},
{WCD939X_LB_IN_SEL_CTL, 0x00},
{WCD939X_LOOP_BACK_MODE, 0x00},
{WCD939X_SWR_DAC_TEST, 0x00},
{WCD939X_SWR_HM_TEST_RX_0, 0x40},
{WCD939X_SWR_HM_TEST_TX_0, 0x40},
{WCD939X_SWR_HM_TEST_RX_1, 0x00},
{WCD939X_SWR_HM_TEST_TX_1, 0x00},
{WCD939X_SWR_HM_TEST_TX_2, 0x00},
{WCD939X_SWR_HM_TEST_0, 0x00},
{WCD939X_SWR_HM_TEST_1, 0x00},
{WCD939X_PAD_CTL_SWR_0, 0x8f},
{WCD939X_PAD_CTL_SWR_1, 0x06},
{WCD939X_I2C_CTL, 0x00},
{WCD939X_CDC_TX_TANGGU_SW_MODE, 0x00},
{WCD939X_EFUSE_TEST_CTL_0, 0x00},
{WCD939X_EFUSE_TEST_CTL_1, 0x00},
{WCD939X_EFUSE_T_DATA_0, 0x00},
{WCD939X_EFUSE_T_DATA_1, 0x00},
{WCD939X_PAD_CTL_PDM_RX0, 0xf1},
{WCD939X_PAD_CTL_PDM_RX1, 0xf1},
{WCD939X_PAD_CTL_PDM_TX0, 0xf1},
{WCD939X_PAD_CTL_PDM_TX1, 0xf1},
{WCD939X_PAD_CTL_PDM_TX2, 0xf1},
{WCD939X_PAD_INP_DIS_0, 0x00},
{WCD939X_PAD_INP_DIS_1, 0x00},
{WCD939X_DRIVE_STRENGTH_0, 0x00},
{WCD939X_DRIVE_STRENGTH_1, 0x00},
{WCD939X_DRIVE_STRENGTH_2, 0x00},
{WCD939X_RX_DATA_EDGE_CTL, 0x1f},
{WCD939X_TX_DATA_EDGE_CTL, 0x80},
{WCD939X_GPIO_MODE, 0x00},
{WCD939X_PIN_CTL_OE, 0x00},
{WCD939X_PIN_CTL_DATA_0, 0x00},
{WCD939X_PIN_CTL_DATA_1, 0x00},
{WCD939X_PIN_STATUS_0, 0x00},
{WCD939X_PIN_STATUS_1, 0x00},
{WCD939X_DIG_DEBUG_CTL, 0x00},
{WCD939X_DIG_DEBUG_EN, 0x00},
{WCD939X_ANA_CSR_DBG_ADD, 0x00},
{WCD939X_ANA_CSR_DBG_CTL, 0x48},
{WCD939X_SSP_DBG, 0x00},
{WCD939X_MODE_STATUS_0, 0x00},
{WCD939X_MODE_STATUS_1, 0x00},
{WCD939X_SPARE_0, 0x00},
{WCD939X_SPARE_1, 0x00},
{WCD939X_SPARE_2, 0x00},
{WCD939X_EFUSE_REG_0, 0x00},
{WCD939X_EFUSE_REG_1, 0xff},
{WCD939X_EFUSE_REG_2, 0xff},
{WCD939X_EFUSE_REG_3, 0xff},
{WCD939X_EFUSE_REG_4, 0xff},
{WCD939X_EFUSE_REG_5, 0xff},
{WCD939X_EFUSE_REG_6, 0xff},
{WCD939X_EFUSE_REG_7, 0xff},
{WCD939X_EFUSE_REG_8, 0xff},
{WCD939X_EFUSE_REG_9, 0xff},
{WCD939X_EFUSE_REG_10, 0xff},
{WCD939X_EFUSE_REG_11, 0xff},
{WCD939X_EFUSE_REG_12, 0xff},
{WCD939X_EFUSE_REG_13, 0xff},
{WCD939X_EFUSE_REG_14, 0xff},
{WCD939X_EFUSE_REG_15, 0xff},
{WCD939X_EFUSE_REG_16, 0xff},
{WCD939X_EFUSE_REG_17, 0xff},
{WCD939X_EFUSE_REG_18, 0xff},
{WCD939X_EFUSE_REG_19, 0xff},
{WCD939X_EFUSE_REG_20, 0x0e},
{WCD939X_EFUSE_REG_21, 0x00},
{WCD939X_EFUSE_REG_22, 0x00},
{WCD939X_EFUSE_REG_23, 0xf6},
{WCD939X_EFUSE_REG_24, 0x18},
{WCD939X_EFUSE_REG_25, 0x00},
{WCD939X_EFUSE_REG_26, 0x00},
{WCD939X_EFUSE_REG_27, 0x00},
{WCD939X_EFUSE_REG_28, 0x00},
{WCD939X_EFUSE_REG_29, 0x0f},
{WCD939X_EFUSE_REG_30, 0x49},
{WCD939X_EFUSE_REG_31, 0x00},
{WCD939X_TX_REQ_FB_CTL_0, 0x88},
{WCD939X_TX_REQ_FB_CTL_1, 0x88},
{WCD939X_TX_REQ_FB_CTL_2, 0x88},
{WCD939X_TX_REQ_FB_CTL_3, 0x88},
{WCD939X_TX_REQ_FB_CTL_4, 0x88},
{WCD939X_DEM_BYPASS_DATA0, 0x55},
{WCD939X_DEM_BYPASS_DATA1, 0x55},
{WCD939X_DEM_BYPASS_DATA2, 0x55},
{WCD939X_DEM_BYPASS_DATA3, 0x01},
{WCD939X_DEM_SECOND_ORDER, 0x03},
{WCD939X_DSM_CTRL, 0x00},
{WCD939X_DSM_0_STATIC_DATA_0, 0x00},
{WCD939X_DSM_0_STATIC_DATA_1, 0x00},
{WCD939X_DSM_0_STATIC_DATA_2, 0x00},
{WCD939X_DSM_0_STATIC_DATA_3, 0x00},
{WCD939X_DSM_1_STATIC_DATA_0, 0x00},
{WCD939X_DSM_1_STATIC_DATA_1, 0x00},
{WCD939X_DSM_1_STATIC_DATA_2, 0x00},
{WCD939X_DSM_1_STATIC_DATA_3, 0x00},
{WCD939X_RX_PAGE, 0x00},
{WCD939X_TOP_CFG0, 0x00},
{WCD939X_HPHL_COMP_WR_LSB, 0x00},
{WCD939X_HPHL_COMP_WR_MSB, 0x00},
{WCD939X_HPHL_COMP_LUT, 0x00},
{WCD939X_HPHL_COMP_RD_LSB, 0x00},
{WCD939X_HPHL_COMP_RD_MSB, 0x00},
{WCD939X_HPHR_COMP_WR_LSB, 0x00},
{WCD939X_HPHR_COMP_WR_MSB, 0x00},
{WCD939X_HPHR_COMP_LUT, 0x00},
{WCD939X_HPHR_COMP_RD_LSB, 0x00},
{WCD939X_HPHR_COMP_RD_MSB, 0x00},
{WCD939X_DSD0_DEBUG_CFG1, 0x05},
{WCD939X_DSD0_DEBUG_CFG2, 0x08},
{WCD939X_DSD0_DEBUG_CFG3, 0x00},
{WCD939X_DSD0_DEBUG_CFG4, 0x00},
{WCD939X_DSD0_DEBUG_CFG5, 0x00},
{WCD939X_DSD0_DEBUG_CFG6, 0x00},
{WCD939X_DSD1_DEBUG_CFG1, 0x03},
{WCD939X_DSD1_DEBUG_CFG2, 0x08},
{WCD939X_DSD1_DEBUG_CFG3, 0x00},
{WCD939X_DSD1_DEBUG_CFG4, 0x00},
{WCD939X_DSD1_DEBUG_CFG5, 0x00},
{WCD939X_DSD1_DEBUG_CFG6, 0x00},
{WCD939X_HPHL_RX_PATH_CFG0, 0x00},
{WCD939X_HPHL_RX_PATH_CFG1, 0x00},
{WCD939X_HPHR_RX_PATH_CFG0, 0x00},
{WCD939X_HPHR_RX_PATH_CFG1, 0x00},
{WCD939X_RX_PATH_CFG2, 0x00},
{WCD939X_HPHL_RX_PATH_SEC0, 0x00},
{WCD939X_HPHL_RX_PATH_SEC1, 0x00},
{WCD939X_HPHL_RX_PATH_SEC2, 0x00},
{WCD939X_HPHL_RX_PATH_SEC3, 0x00},
{WCD939X_HPHR_RX_PATH_SEC0, 0x00},
{WCD939X_HPHR_RX_PATH_SEC1, 0x00},
{WCD939X_HPHR_RX_PATH_SEC2, 0x00},
{WCD939X_HPHR_RX_PATH_SEC3, 0x00},
{WCD939X_RX_PATH_SEC4, 0x00},
{WCD939X_RX_PATH_SEC5, 0x00},
{WCD939X_CTL0, 0x60},
{WCD939X_CTL1, 0xdb},
{WCD939X_CTL2, 0xff},
{WCD939X_CTL3, 0x35},
{WCD939X_CTL4, 0xff},
{WCD939X_CTL5, 0x00},
{WCD939X_CTL6, 0x01},
{WCD939X_CTL7, 0x08},
{WCD939X_CTL8, 0x00},
{WCD939X_CTL9, 0x00},
{WCD939X_CTL10, 0x06},
{WCD939X_CTL11, 0x12},
{WCD939X_CTL12, 0x1e},
{WCD939X_CTL13, 0x2a},
{WCD939X_CTL14, 0x36},
{WCD939X_CTL15, 0x3c},
{WCD939X_CTL16, 0xc4},
{WCD939X_CTL17, 0x00},
{WCD939X_CTL18, 0x0c},
{WCD939X_CTL19, 0x16},
{WCD939X_R_CTL0, 0x60},
{WCD939X_R_CTL1, 0xdb},
{WCD939X_R_CTL2, 0xff},
{WCD939X_R_CTL3, 0x35},
{WCD939X_R_CTL4, 0xff},
{WCD939X_R_CTL5, 0x00},
{WCD939X_R_CTL6, 0x01},
{WCD939X_R_CTL7, 0x08},
{WCD939X_R_CTL8, 0x00},
{WCD939X_R_CTL9, 0x00},
{WCD939X_R_CTL10, 0x06},
{WCD939X_R_CTL11, 0x12},
{WCD939X_R_CTL12, 0x1e},
{WCD939X_R_CTL13, 0x2a},
{WCD939X_R_CTL14, 0x36},
{WCD939X_R_CTL15, 0x3c},
{WCD939X_R_CTL16, 0xc4},
{WCD939X_R_CTL17, 0x00},
{WCD939X_R_CTL18, 0x0c},
{WCD939X_R_CTL19, 0x16},
{WCD939X_PATH_CTL, 0x00},
{WCD939X_CFG0, 0x07},
{WCD939X_CFG1, 0x3c},
{WCD939X_CFG2, 0x00},
{WCD939X_CFG3, 0x00},
{WCD939X_DSD_HPHL_PATH_CTL, 0x00},
{WCD939X_DSD_HPHL_CFG0, 0x00},
{WCD939X_DSD_HPHL_CFG1, 0x00},
{WCD939X_DSD_HPHL_CFG2, 0x22},
{WCD939X_DSD_HPHL_CFG3, 0x00},
{WCD939X_CFG4, 0x1a},
{WCD939X_CFG5, 0x00},
{WCD939X_DSD_HPHR_PATH_CTL, 0x00},
{WCD939X_DSD_HPHR_CFG0, 0x00},
{WCD939X_DSD_HPHR_CFG1, 0x00},
{WCD939X_DSD_HPHR_CFG2, 0x22},
{WCD939X_DSD_HPHR_CFG3, 0x00},
{WCD939X_DSD_HPHR_CFG4, 0x1a},
{WCD939X_DSD_HPHR_CFG5, 0x00},
};
static bool wcd939x_readable_register(struct device *dev, unsigned int reg)
{
if (reg <= WCD939X_BASE + 1)
return 0;
return wcd939x_reg_access[WCD939X_REG(reg)] & RD_REG;
}
static bool wcd939x_writeable_register(struct device *dev, unsigned int reg)
{
if (reg <= WCD939X_BASE + 1)
return 0;
return wcd939x_reg_access[WCD939X_REG(reg)] & WR_REG;
}
static bool wcd939x_volatile_register(struct device *dev, unsigned int reg)
{
if (reg <= WCD939X_BASE + 1)
return 0;
return ((wcd939x_reg_access[WCD939X_REG(reg)] & RD_REG) &&
!(wcd939x_reg_access[WCD939X_REG(reg)] & WR_REG));
}
struct regmap_config wcd939x_regmap_config = {
.reg_bits = 16,
.val_bits = 8,
.cache_type = REGCACHE_RBTREE,
.reg_defaults = wcd939x_defaults,
.num_reg_defaults = ARRAY_SIZE(wcd939x_defaults),
.max_register = WCD939X_MAX_REGISTER,
.volatile_reg = wcd939x_volatile_register,
.readable_reg = wcd939x_readable_register,
.writeable_reg = wcd939x_writeable_register,
.reg_format_endian = REGMAP_ENDIAN_NATIVE,
.val_format_endian = REGMAP_ENDIAN_NATIVE,
.can_multi_write = true,
.use_single_read = true,
};

427
asoc/codecs/wcd939x/wcd939x-slave.c Normal file
Näytä tiedosto

@@ -0,0 +1,427 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/component.h>
#include <soc/soundwire.h>
#ifdef CONFIG_DEBUG_FS
#include <linux/debugfs.h>
#include <linux/uaccess.h>
#define SWR_SLV_MAX_REG_ADDR 0x2009
#define SWR_SLV_START_REG_ADDR 0x40
#define SWR_SLV_MAX_BUF_LEN 20
#define BYTES_PER_LINE 12
#define SWR_SLV_RD_BUF_LEN 8
#define SWR_SLV_WR_BUF_LEN 32
#define SWR_SLV_MAX_DEVICES 2
#endif /* CONFIG_DEBUG_FS */
#define SWR_MAX_RETRY 5
struct wcd939x_slave_priv {
struct swr_device *swr_slave;
#ifdef CONFIG_DEBUG_FS
struct dentry *debugfs_wcd939x_dent;
struct dentry *debugfs_peek;
struct dentry *debugfs_poke;
struct dentry *debugfs_reg_dump;
unsigned int read_data;
#endif
};
#ifdef CONFIG_DEBUG_FS
static int codec_debug_open(struct inode *inode, struct file *file)
{
file->private_data = inode->i_private;
return 0;
}
static int get_parameters(char *buf, u32 *param1, int num_of_par)
{
char *token = NULL;
int base = 0, cnt = 0;
token = strsep(&buf, " ");
for (cnt = 0; cnt < num_of_par; cnt++) {
if (token) {
if ((token[1] == 'x') || (token[1] == 'X'))
base = 16;
else
base = 10;
if (kstrtou32(token, base, &param1[cnt]) != 0)
return -EINVAL;
token = strsep(&buf, " ");
} else {
return -EINVAL;
}
}
return 0;
}
static bool is_swr_slv_reg_readable(int reg)
{
int ret = true;
if (((reg > 0x46) && (reg < 0x4A)) ||
((reg > 0x4A) && (reg < 0x50)) ||
((reg > 0x55) && (reg < 0xD0)) ||
((reg > 0xD0) && (reg < 0xE0)) ||
((reg > 0xE0) && (reg < 0xF0)) ||
((reg > 0xF0) && (reg < 0x100)) ||
((reg > 0x105) && (reg < 0x120)) ||
((reg > 0x205) && (reg < 0x220)) ||
((reg > 0x305) && (reg < 0x320)) ||
((reg > 0x405) && (reg < 0x420)) ||
((reg > 0x128) && (reg < 0x130)) ||
((reg > 0x228) && (reg < 0x230)) ||
((reg > 0x328) && (reg < 0x330)) ||
((reg > 0x428) && (reg < 0x430)) ||
((reg > 0x138) && (reg < 0x205)) ||
((reg > 0x238) && (reg < 0x305)) ||
((reg > 0x338) && (reg < 0x405)) ||
((reg > 0x405) && (reg < 0xF00)) ||
((reg > 0xF05) && (reg < 0xF20)) ||
((reg > 0xF25) && (reg < 0xF30)) ||
((reg > 0xF35) && (reg < 0x2000)))
ret = false;
return ret;
}
static ssize_t wcd939x_swrslave_reg_show(struct swr_device *pdev,
char __user *ubuf,
size_t count, loff_t *ppos)
{
int i, reg_val, len;
ssize_t total = 0;
char tmp_buf[SWR_SLV_MAX_BUF_LEN];
if (!ubuf || !ppos)
return 0;
for (i = (((int) *ppos/BYTES_PER_LINE) + SWR_SLV_START_REG_ADDR);
i <= SWR_SLV_MAX_REG_ADDR; i++) {
if (!is_swr_slv_reg_readable(i))
continue;
swr_read(pdev, pdev->dev_num, i, &reg_val, 1);
len = snprintf(tmp_buf, sizeof(tmp_buf), "0x%.3x: 0x%.2x\n", i,
(reg_val & 0xFF));
if (((total + len) >= count - 1) || (len < 0))
break;
if (copy_to_user((ubuf + total), tmp_buf, len)) {
pr_err_ratelimited("%s: fail to copy reg dump\n", __func__);
total = -EFAULT;
goto copy_err;
}
total += len;
*ppos += len;
}
copy_err:
*ppos = SWR_SLV_MAX_REG_ADDR * BYTES_PER_LINE;
return total;
}
static ssize_t codec_debug_dump(struct file *file, char __user *ubuf,
size_t count, loff_t *ppos)
{
struct swr_device *pdev;
if (!count || !file || !ppos || !ubuf)
return -EINVAL;
pdev = file->private_data;
if (!pdev)
return -EINVAL;
if (*ppos < 0)
return -EINVAL;
return wcd939x_swrslave_reg_show(pdev, ubuf, count, ppos);
}
static ssize_t codec_debug_read(struct file *file, char __user *ubuf,
size_t count, loff_t *ppos)
{
char lbuf[SWR_SLV_RD_BUF_LEN];
struct swr_device *pdev = NULL;
struct wcd939x_slave_priv *wcd939x_slave = NULL;
if (!count || !file || !ppos || !ubuf)
return -EINVAL;
pdev = file->private_data;
if (!pdev)
return -EINVAL;
wcd939x_slave = swr_get_dev_data(pdev);
if (!wcd939x_slave)
return -EINVAL;
if (*ppos < 0)
return -EINVAL;
snprintf(lbuf, sizeof(lbuf), "0x%x\n",
(wcd939x_slave->read_data & 0xFF));
return simple_read_from_buffer(ubuf, count, ppos, lbuf,
strnlen(lbuf, 7));
}
static ssize_t codec_debug_peek_write(struct file *file,
const char __user *ubuf, size_t cnt, loff_t *ppos)
{
char lbuf[SWR_SLV_WR_BUF_LEN];
int rc = 0;
u32 param[5];
struct swr_device *pdev = NULL;
struct wcd939x_slave_priv *wcd939x_slave = NULL;
if (!cnt || !file || !ppos || !ubuf)
return -EINVAL;
pdev = file->private_data;
if (!pdev)
return -EINVAL;
wcd939x_slave = swr_get_dev_data(pdev);
if (!wcd939x_slave)
return -EINVAL;
if (*ppos < 0)
return -EINVAL;
if (cnt > sizeof(lbuf) - 1)
return -EINVAL;
rc = copy_from_user(lbuf, ubuf, cnt);
if (rc)
return -EFAULT;
lbuf[cnt] = '\0';
rc = get_parameters(lbuf, param, 1);
if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) && (rc == 0)))
return -EINVAL;
swr_read(pdev, pdev->dev_num, param[0], &wcd939x_slave->read_data, 1);
if (rc == 0)
rc = cnt;
else
pr_err_ratelimited("%s: rc = %d\n", __func__, rc);
return rc;
}
static ssize_t codec_debug_write(struct file *file,
const char __user *ubuf, size_t cnt, loff_t *ppos)
{
char lbuf[SWR_SLV_WR_BUF_LEN];
int rc = 0;
u32 param[5];
struct swr_device *pdev;
if (!file || !ppos || !ubuf)
return -EINVAL;
pdev = file->private_data;
if (!pdev)
return -EINVAL;
if (cnt > sizeof(lbuf) - 1)
return -EINVAL;
rc = copy_from_user(lbuf, ubuf, cnt);
if (rc)
return -EFAULT;
lbuf[cnt] = '\0';
rc = get_parameters(lbuf, param, 2);
if (!((param[0] <= SWR_SLV_MAX_REG_ADDR) &&
(param[1] <= 0xFF) && (rc == 0)))
return -EINVAL;
swr_write(pdev, pdev->dev_num, param[0], &param[1]);
if (rc == 0)
rc = cnt;
else
pr_err_ratelimited("%s: rc = %d\n", __func__, rc);
return rc;
}
static const struct file_operations codec_debug_write_ops = {
.open = codec_debug_open,
.write = codec_debug_write,
};
static const struct file_operations codec_debug_read_ops = {
.open = codec_debug_open,
.read = codec_debug_read,
.write = codec_debug_peek_write,
};
static const struct file_operations codec_debug_dump_ops = {
.open = codec_debug_open,
.read = codec_debug_dump,
};
#endif
static int wcd939x_slave_bind(struct device *dev,
struct device *master, void *data)
{
int ret = 0;
uint8_t devnum = 0;
struct swr_device *pdev = to_swr_device(dev);
int retry = SWR_MAX_RETRY;
if (!pdev) {
pr_err_ratelimited("%s: invalid swr device handle\n", __func__);
return -EINVAL;
}
do {
/* Add delay for soundwire enumeration */
usleep_range(100, 110);
ret = swr_get_logical_dev_num(pdev, pdev->addr, &devnum);
} while (ret && --retry);
if (ret) {
dev_dbg(&pdev->dev,
"%s get devnum %d for dev addr %llx failed\n",
__func__, devnum, pdev->addr);
ret = -EPROBE_DEFER;
return ret;
}
pdev->dev_num = devnum;
return ret;
}
static void wcd939x_slave_unbind(struct device *dev,
struct device *master, void *data)
{
struct wcd939x_slave_priv *wcd939x_slave = NULL;
struct swr_device *pdev = to_swr_device(dev);
wcd939x_slave = swr_get_dev_data(pdev);
if (!wcd939x_slave) {
dev_err_ratelimited(&pdev->dev, "%s: wcd939x_slave is NULL\n", __func__);
return;
}
}
static const struct swr_device_id wcd939x_swr_id[] = {
{"wcd939x-slave", 0},
{}
};
static const struct of_device_id wcd939x_swr_dt_match[] = {
{
.compatible = "qcom,wcd939x-slave",
},
{}
};
static const struct component_ops wcd939x_slave_comp_ops = {
.bind = wcd939x_slave_bind,
.unbind = wcd939x_slave_unbind,
};
static int wcd939x_swr_probe(struct swr_device *pdev)
{
struct wcd939x_slave_priv *wcd939x_slave = NULL;
wcd939x_slave = devm_kzalloc(&pdev->dev,
sizeof(struct wcd939x_slave_priv), GFP_KERNEL);
if (!wcd939x_slave)
return -ENOMEM;
swr_set_dev_data(pdev, wcd939x_slave);
wcd939x_slave->swr_slave = pdev;
#ifdef CONFIG_DEBUG_FS
if (!wcd939x_slave->debugfs_wcd939x_dent) {
wcd939x_slave->debugfs_wcd939x_dent = debugfs_create_dir(
dev_name(&pdev->dev), 0);
if (!IS_ERR(wcd939x_slave->debugfs_wcd939x_dent)) {
wcd939x_slave->debugfs_peek =
debugfs_create_file("swrslave_peek",
S_IFREG | 0444,
wcd939x_slave->debugfs_wcd939x_dent,
(void *) pdev,
&codec_debug_read_ops);
wcd939x_slave->debugfs_poke =
debugfs_create_file("swrslave_poke",
S_IFREG | 0444,
wcd939x_slave->debugfs_wcd939x_dent,
(void *) pdev,
&codec_debug_write_ops);
wcd939x_slave->debugfs_reg_dump =
debugfs_create_file(
"swrslave_reg_dump",
S_IFREG | 0444,
wcd939x_slave->debugfs_wcd939x_dent,
(void *) pdev,
&codec_debug_dump_ops);
}
}
#endif
return component_add(&pdev->dev, &wcd939x_slave_comp_ops);
}
static int wcd939x_swr_remove(struct swr_device *pdev)
{
#ifdef CONFIG_DEBUG_FS
struct wcd939x_slave_priv *wcd939x_slave = swr_get_dev_data(pdev);
if (wcd939x_slave) {
debugfs_remove_recursive(wcd939x_slave->debugfs_wcd939x_dent);
wcd939x_slave->debugfs_wcd939x_dent = NULL;
}
#endif
component_del(&pdev->dev, &wcd939x_slave_comp_ops);
swr_set_dev_data(pdev, NULL);
swr_remove_device(pdev);
return 0;
}
static struct swr_driver wcd939x_slave_driver = {
.driver = {
.name = "wcd939x-slave",
.owner = THIS_MODULE,
.of_match_table = wcd939x_swr_dt_match,
},
.probe = wcd939x_swr_probe,
.remove = wcd939x_swr_remove,
.id_table = wcd939x_swr_id,
};
static int __init wcd939x_slave_init(void)
{
return swr_driver_register(&wcd939x_slave_driver);
}
static void __exit wcd939x_slave_exit(void)
{
swr_driver_unregister(&wcd939x_slave_driver);
}
module_init(wcd939x_slave_init);
module_exit(wcd939x_slave_exit);
MODULE_DESCRIPTION("WCD939X Swr Slave driver");
MODULE_LICENSE("GPL v2");

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asoc/codecs/wcd939x/wcd939x-tables.c Normal file
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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2018, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <linux/regmap.h>
#include <linux/device.h>
#include "wcd939x-registers.h"
const u8 wcd939x_reg_access[WCD939X_NUM_REGISTERS] = {
[WCD939X_REG(WCD939X_ANA_PAGE)] = RD_WR_REG,
[WCD939X_REG(WCD939X_BIAS)] = RD_WR_REG,
[WCD939X_REG(WCD939X_RX_SUPPLIES)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPH)] = RD_WR_REG,
[WCD939X_REG(WCD939X_EAR)] = RD_WR_REG,
[WCD939X_REG(WCD939X_EAR_COMPANDER_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TX_CH1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TX_CH2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TX_CH3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TX_CH4)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MICB1_MICB2_DSP_EN_LOGIC)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MICB3_DSP_EN_LOGIC)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MBHC_MECH)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MBHC_ELECT)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MBHC_ZDET)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MBHC_RESULT_1)] = RD_REG,
[WCD939X_REG(WCD939X_MBHC_RESULT_2)] = RD_REG,
[WCD939X_REG(WCD939X_MBHC_RESULT_3)] = RD_REG,
[WCD939X_REG(WCD939X_MBHC_BTN0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MBHC_BTN1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MBHC_BTN2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MBHC_BTN3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MBHC_BTN4)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MBHC_BTN5)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MBHC_BTN6)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MBHC_BTN7)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MICB1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MICB2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MICB2_RAMP)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MICB3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MICB4)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_VBG_FINE_ADJ)] = RD_WR_REG,
[WCD939X_REG(WCD939X_VDDCX_ADJUST)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DISABLE_LDOL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL_CLK)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL_ANA)] = RD_WR_REG,
[WCD939X_REG(WCD939X_ZDET_VNEG_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_ZDET_BIAS_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL_BCS)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MOISTURE_DET_FSM_STATUS)] = RD_REG,
[WCD939X_REG(WCD939X_TEST_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MODE)] = RD_WR_REG,
[WCD939X_REG(WCD939X_LDOH_BIAS)] = RD_WR_REG,
[WCD939X_REG(WCD939X_STB_LOADS)] = RD_WR_REG,
[WCD939X_REG(WCD939X_SLOWRAMP)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TEST_CTL_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TEST_CTL_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TEST_CTL_3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MICB2_TEST_CTL_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MICB2_TEST_CTL_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MICB2_TEST_CTL_3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MICB3_TEST_CTL_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MICB3_TEST_CTL_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MICB3_TEST_CTL_3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MICB4_TEST_CTL_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MICB4_TEST_CTL_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MICB4_TEST_CTL_3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_ADC_VCM)] = RD_WR_REG,
[WCD939X_REG(WCD939X_BIAS_ATEST)] = RD_WR_REG,
[WCD939X_REG(WCD939X_SPARE1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_SPARE2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXFE_DIV_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXFE_DIV_START)] = RD_WR_REG,
[WCD939X_REG(WCD939X_SPARE3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_SPARE4)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TEST_EN)] = RD_WR_REG,
[WCD939X_REG(WCD939X_ADC_IB)] = RD_WR_REG,
[WCD939X_REG(WCD939X_ATEST_REFCTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TX_1_2_TEST_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TEST_BLK_EN1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXFE1_CLKDIV)] = RD_WR_REG,
[WCD939X_REG(WCD939X_SAR2_ERR)] = RD_REG,
[WCD939X_REG(WCD939X_SAR1_ERR)] = RD_REG,
[WCD939X_REG(WCD939X_TX_3_4_TEST_EN)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TX_3_4_ADC_IB)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TX_3_4_ATEST_REFCTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TX_3_4_TEST_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TEST_BLK_EN3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXFE3_CLKDIV)] = RD_WR_REG,
[WCD939X_REG(WCD939X_SAR4_ERR)] = RD_REG,
[WCD939X_REG(WCD939X_SAR3_ERR)] = RD_REG,
[WCD939X_REG(WCD939X_TEST_BLK_EN2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXFE2_CLKDIV)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TX_3_4_SPARE1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TEST_BLK_EN4)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXFE4_CLKDIV)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TX_3_4_SPARE2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MODE_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MODE_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MODE_3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTRL_VCL_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTRL_VCL_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTRL_CCL_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTRL_CCL_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTRL_CCL_3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTRL_CCL_4)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTRL_CCL_5)] = RD_WR_REG,
[WCD939X_REG(WCD939X_BUCK_TMUX_A_D)] = RD_WR_REG,
[WCD939X_REG(WCD939X_BUCK_SW_DRV_CNTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_SPARE)] = RD_WR_REG,
[WCD939X_REG(WCD939X_EN)] = RD_WR_REG,
[WCD939X_REG(WCD939X_VNEG_CTRL_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_VNEG_CTRL_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_VNEG_CTRL_3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_VNEG_CTRL_4)] = RD_WR_REG,
[WCD939X_REG(WCD939X_VNEG_CTRL_5)] = RD_WR_REG,
[WCD939X_REG(WCD939X_VNEG_CTRL_6)] = RD_WR_REG,
[WCD939X_REG(WCD939X_VNEG_CTRL_7)] = RD_WR_REG,
[WCD939X_REG(WCD939X_VNEG_CTRL_8)] = RD_WR_REG,
[WCD939X_REG(WCD939X_VNEG_CTRL_9)] = RD_WR_REG,
[WCD939X_REG(WCD939X_VNEGDAC_CTRL_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_VNEGDAC_CTRL_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_VNEGDAC_CTRL_3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTRL_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_FLYBACK_TEST_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_AUX_SW_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PA_AUX_IN_CONN)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TIMER_DIV)] = RD_WR_REG,
[WCD939X_REG(WCD939X_OCP_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_OCP_COUNT)] = RD_WR_REG,
[WCD939X_REG(WCD939X_BIAS_EAR_DAC)] = RD_WR_REG,
[WCD939X_REG(WCD939X_BIAS_EAR_AMP)] = RD_WR_REG,
[WCD939X_REG(WCD939X_BIAS_HPH_LDO)] = RD_WR_REG,
[WCD939X_REG(WCD939X_BIAS_HPH_PA)] = RD_WR_REG,
[WCD939X_REG(WCD939X_BIAS_HPH_RDACBUFF_CNP2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_BIAS_HPH_RDAC_LDO)] = RD_WR_REG,
[WCD939X_REG(WCD939X_BIAS_HPH_CNP1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_BIAS_HPH_LOWPOWER)] = RD_WR_REG,
[WCD939X_REG(WCD939X_BIAS_AUX_DAC)] = RD_WR_REG,
[WCD939X_REG(WCD939X_BIAS_AUX_AMP)] = RD_WR_REG,
[WCD939X_REG(WCD939X_BIAS_VNEGDAC_BLEEDER)] = RD_WR_REG,
[WCD939X_REG(WCD939X_BIAS_MISC)] = RD_WR_REG,
[WCD939X_REG(WCD939X_BIAS_BUCK_RST)] = RD_WR_REG,
[WCD939X_REG(WCD939X_BIAS_BUCK_VREF_ERRAMP)] = RD_WR_REG,
[WCD939X_REG(WCD939X_BIAS_FLYB_ERRAMP)] = RD_WR_REG,
[WCD939X_REG(WCD939X_BIAS_FLYB_BUFF)] = RD_WR_REG,
[WCD939X_REG(WCD939X_BIAS_FLYB_MID_RST)] = RD_WR_REG,
[WCD939X_REG(WCD939X_L_STATUS)] = RD_REG,
[WCD939X_REG(WCD939X_R_STATUS)] = RD_REG,
[WCD939X_REG(WCD939X_CNP_EN)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CNP_WG_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CNP_WG_TIME)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPH_OCP_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_AUTO_CHOP)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CHOP_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PA_CTL1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PA_CTL2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_L_EN)] = RD_WR_REG,
[WCD939X_REG(WCD939X_L_TEST)] = RD_WR_REG,
[WCD939X_REG(WCD939X_L_ATEST)] = RD_WR_REG,
[WCD939X_REG(WCD939X_R_EN)] = RD_WR_REG,
[WCD939X_REG(WCD939X_R_TEST)] = RD_WR_REG,
[WCD939X_REG(WCD939X_R_ATEST)] = RD_WR_REG,
[WCD939X_REG(WCD939X_RDAC_CLK_CTL1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_RDAC_CLK_CTL2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_RDAC_LDO_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_RDAC_CHOP_CLK_LP_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_REFBUFF_UHQA_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_REFBUFF_LP_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_L_DAC_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_R_DAC_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPHLR_SURGE_COMP_SEL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPHLR_SURGE_EN)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPHLR_SURGE_MISC1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPHLR_SURGE_STATUS)] = RD_REG,
[WCD939X_REG(WCD939X_EAR_EN_REG)] = RD_WR_REG,
[WCD939X_REG(WCD939X_EAR_PA_CON)] = RD_WR_REG,
[WCD939X_REG(WCD939X_EAR_SP_CON)] = RD_WR_REG,
[WCD939X_REG(WCD939X_EAR_DAC_CON)] = RD_WR_REG,
[WCD939X_REG(WCD939X_EAR_CNP_FSM_CON)] = RD_WR_REG,
[WCD939X_REG(WCD939X_EAR_TEST_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_STATUS_REG_1)] = RD_REG,
[WCD939X_REG(WCD939X_STATUS_REG_2)] = RD_REG,
[WCD939X_REG(WCD939X_ANA_NEW_PAGE)] = RD_WR_REG,
[WCD939X_REG(WCD939X_ANA_HPH2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_ANA_HPH3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_SLEEP_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_WATCHDOG_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_ELECT_REM_CLAMP_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PLUG_DETECT_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_ZDET_ANA_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_ZDET_RAMP_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_FSM_STATUS)] = RD_REG,
[WCD939X_REG(WCD939X_ADC_RESULT)] = RD_REG,
[WCD939X_REG(WCD939X_TX_CH12_MUX)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TX_CH34_MUX)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DIE_CRK_DET_EN)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DIE_CRK_DET_OUT)] = RD_REG,
[WCD939X_REG(WCD939X_RDAC_GAIN_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PA_GAIN_CTL_L)] = RD_WR_REG,
[WCD939X_REG(WCD939X_RDAC_VREF_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_RDAC_OVERRIDE_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PA_GAIN_CTL_R)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PA_MISC1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PA_MISC2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PA_RDAC_MISC)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPH_TIMER1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPH_TIMER2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPH_TIMER3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPH_TIMER4)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PA_RDAC_MISC2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PA_RDAC_MISC3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_RDAC_HD2_CTL_L)] = RD_WR_REG,
[WCD939X_REG(WCD939X_RDAC_HD2_CTL_R)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPH_RDAC_BIAS_LOHIFI)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPH_RDAC_BIAS_ULP)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPH_RDAC_LDO_LP)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MOISTURE_DET_DC_CTRL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MOISTURE_DET_POLLING_CTRL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MECH_DET_CURRENT)] = RD_WR_REG,
[WCD939X_REG(WCD939X_ZDET_CLK_AND_MOISTURE_CTL_NEW)] = RD_WR_REG,
[WCD939X_REG(WCD939X_EAR_CHOPPER_CON)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CNP_VCM_CON1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CNP_VCM_CON2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_EAR_DYNAMIC_BIAS)] = RD_WR_REG,
[WCD939X_REG(WCD939X_WATCHDOG_CTL_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_WATCHDOG_CTL_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DIE_CRK_DET_INT1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DIE_CRK_DET_INT2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXFE_DIVSTOP_L2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXFE_DIVSTOP_L1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXFE_DIVSTOP_L0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXFE_DIVSTOP_ULP1P2M)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXFE_DIVSTOP_ULP0P6M)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXFE_ICTRL_STG1_L2L1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXFE_ICTRL_STG1_L0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXFE_ICTRL_STG1_ULP)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXFE_ICTRL_STG2MAIN_L2L1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXFE_ICTRL_STG2MAIN_L0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXFE_ICTRL_STG2MAIN_ULP)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXFE_ICTRL_STG2CASC_L2L1L0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXFE_ICTRL_STG2CASC_ULP)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXADC_SCBIAS_L2L1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXADC_SCBIAS_L0ULP)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXADC_INT_L2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXADC_INT_L1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXADC_INT_L0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TXADC_INT_ULP)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DIGITAL_PAGE)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CHIP_ID0)] = RD_REG,
[WCD939X_REG(WCD939X_CHIP_ID1)] = RD_REG,
[WCD939X_REG(WCD939X_CHIP_ID2)] = RD_REG,
[WCD939X_REG(WCD939X_CHIP_ID3)] = RD_REG,
[WCD939X_REG(WCD939X_SWR_TX_CLK_RATE)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_RST_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TOP_CLK_CFG)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_ANA_CLK_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_DIG_CLK_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_SWR_RST_EN)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_PATH_MODE)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_RX_RST)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_RX0_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_RX1_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_RX2_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_TX_ANA_MODE_0_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_TX_ANA_MODE_2_3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_COMP_CTL_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_ANA_TX_CLK_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_DSM_A1_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_DSM_A1_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_DSM_A2_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_DSM_A2_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_DSM_A3_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_DSM_A3_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_DSM_A4_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_DSM_A4_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_DSM_A5_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_DSM_A5_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_DSM_A6_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_DSM_A7_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_DSM_C_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_DSM_C_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_DSM_C_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_DSM_C_3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_DSM_R1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_DSM_R2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_DSM_R3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_DSM_R4)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_DSM_R5)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_DSM_R6)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_DSM_R7)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_DSM_A1_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_DSM_A1_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_DSM_A2_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_DSM_A2_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_DSM_A3_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_DSM_A3_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_DSM_A4_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_DSM_A4_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_DSM_A5_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_DSM_A5_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_DSM_A6_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_DSM_A7_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_DSM_C_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_DSM_C_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_DSM_C_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_DSM_C_3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_DSM_R1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_DSM_R2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_DSM_R3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_DSM_R4)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_DSM_R5)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_DSM_R6)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_DSM_R7)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_GAIN_RX_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_GAIN_RX_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_GAIN_DSD_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_GAIN_DSD_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_GAIN_DSD_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_GAIN_DSD_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_GAIN_DSD_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_GAIN_DSD_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_HPH_GAIN_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_GAIN_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_EAR_PATH_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_SWR_CLH)] = RD_WR_REG,
[WCD939X_REG(WCD939X_SWR_CLH_BYP)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_TX0_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_TX1_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_TX2_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_TX_RST)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_REQ_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_RST)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_AMIC_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_DMIC_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_DMIC1_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_DMIC2_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_DMIC3_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_DMIC4_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_EFUSE_PRG_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_EFUSE_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_DMIC_RATE_1_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_DMIC_RATE_3_4)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PDM_WD_CTL0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PDM_WD_CTL1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PDM_WD_CTL2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_INTR_MODE)] = RD_WR_REG,
[WCD939X_REG(WCD939X_INTR_MASK_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_INTR_MASK_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_INTR_MASK_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_INTR_STATUS_0)] = RD_REG,
[WCD939X_REG(WCD939X_INTR_STATUS_1)] = RD_REG,
[WCD939X_REG(WCD939X_INTR_STATUS_2)] = RD_REG,
[WCD939X_REG(WCD939X_INTR_CLEAR_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_INTR_CLEAR_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_INTR_CLEAR_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_INTR_LEVEL_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_INTR_LEVEL_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_INTR_LEVEL_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_INTR_SET_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_INTR_SET_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_INTR_SET_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_INTR_TEST_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_INTR_TEST_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_INTR_TEST_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TX_MODE_DBG_EN)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TX_MODE_DBG_0_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TX_MODE_DBG_2_3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_LB_IN_SEL_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_LOOP_BACK_MODE)] = RD_WR_REG,
[WCD939X_REG(WCD939X_SWR_DAC_TEST)] = RD_WR_REG,
[WCD939X_REG(WCD939X_SWR_HM_TEST_RX_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_SWR_HM_TEST_TX_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_SWR_HM_TEST_RX_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_SWR_HM_TEST_TX_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_SWR_HM_TEST_TX_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_SWR_HM_TEST_0)] = RD_REG,
[WCD939X_REG(WCD939X_SWR_HM_TEST_1)] = RD_REG,
[WCD939X_REG(WCD939X_PAD_CTL_SWR_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PAD_CTL_SWR_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_I2C_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CDC_TX_TANGGU_SW_MODE)] = RD_WR_REG,
[WCD939X_REG(WCD939X_EFUSE_TEST_CTL_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_EFUSE_TEST_CTL_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_EFUSE_T_DATA_0)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_T_DATA_1)] = RD_REG,
[WCD939X_REG(WCD939X_PAD_CTL_PDM_RX0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PAD_CTL_PDM_RX1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PAD_CTL_PDM_TX0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PAD_CTL_PDM_TX1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PAD_CTL_PDM_TX2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PAD_INP_DIS_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PAD_INP_DIS_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DRIVE_STRENGTH_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DRIVE_STRENGTH_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DRIVE_STRENGTH_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_RX_DATA_EDGE_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TX_DATA_EDGE_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_GPIO_MODE)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PIN_CTL_OE)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PIN_CTL_DATA_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PIN_CTL_DATA_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PIN_STATUS_0)] = RD_REG,
[WCD939X_REG(WCD939X_PIN_STATUS_1)] = RD_REG,
[WCD939X_REG(WCD939X_DIG_DEBUG_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DIG_DEBUG_EN)] = RD_WR_REG,
[WCD939X_REG(WCD939X_ANA_CSR_DBG_ADD)] = RD_WR_REG,
[WCD939X_REG(WCD939X_ANA_CSR_DBG_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_SSP_DBG)] = RD_WR_REG,
[WCD939X_REG(WCD939X_MODE_STATUS_0)] = RD_REG,
[WCD939X_REG(WCD939X_MODE_STATUS_1)] = RD_REG,
[WCD939X_REG(WCD939X_SPARE_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_SPARE_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_SPARE_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_0)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_1)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_2)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_3)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_4)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_5)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_6)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_7)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_8)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_9)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_10)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_11)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_12)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_13)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_14)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_15)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_16)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_17)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_18)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_19)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_20)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_21)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_22)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_23)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_24)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_25)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_26)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_27)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_28)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_29)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_30)] = RD_REG,
[WCD939X_REG(WCD939X_EFUSE_REG_31)] = RD_REG,
[WCD939X_REG(WCD939X_TX_REQ_FB_CTL_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TX_REQ_FB_CTL_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TX_REQ_FB_CTL_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TX_REQ_FB_CTL_3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TX_REQ_FB_CTL_4)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DEM_BYPASS_DATA0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DEM_BYPASS_DATA1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DEM_BYPASS_DATA2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DEM_BYPASS_DATA3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DEM_SECOND_ORDER)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSM_CTRL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSM_0_STATIC_DATA_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSM_0_STATIC_DATA_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSM_0_STATIC_DATA_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSM_0_STATIC_DATA_3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSM_1_STATIC_DATA_0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSM_1_STATIC_DATA_1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSM_1_STATIC_DATA_2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSM_1_STATIC_DATA_3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_RX_PAGE)] = RD_WR_REG,
[WCD939X_REG(WCD939X_TOP_CFG0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPHL_COMP_WR_LSB)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPHL_COMP_WR_MSB)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPHL_COMP_LUT)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPHL_COMP_RD_LSB)] = RD_REG,
[WCD939X_REG(WCD939X_HPHL_COMP_RD_MSB)] = RD_REG,
[WCD939X_REG(WCD939X_HPHR_COMP_WR_LSB)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPHR_COMP_WR_MSB)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPHR_COMP_LUT)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPHR_COMP_RD_LSB)] = RD_REG,
[WCD939X_REG(WCD939X_HPHR_COMP_RD_MSB)] = RD_REG,
[WCD939X_REG(WCD939X_DSD0_DEBUG_CFG1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSD0_DEBUG_CFG2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSD0_DEBUG_CFG3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSD0_DEBUG_CFG4)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSD0_DEBUG_CFG5)] = RD_REG,
[WCD939X_REG(WCD939X_DSD0_DEBUG_CFG6)] = RD_REG,
[WCD939X_REG(WCD939X_DSD1_DEBUG_CFG1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSD1_DEBUG_CFG2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSD1_DEBUG_CFG3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSD1_DEBUG_CFG4)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSD1_DEBUG_CFG5)] = RD_REG,
[WCD939X_REG(WCD939X_DSD1_DEBUG_CFG6)] = RD_REG,
[WCD939X_REG(WCD939X_HPHL_RX_PATH_CFG0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPHL_RX_PATH_CFG1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPHR_RX_PATH_CFG0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPHR_RX_PATH_CFG1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_RX_PATH_CFG2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPHL_RX_PATH_SEC0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPHL_RX_PATH_SEC1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPHL_RX_PATH_SEC2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPHL_RX_PATH_SEC3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPHR_RX_PATH_SEC0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPHR_RX_PATH_SEC1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPHR_RX_PATH_SEC2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_HPHR_RX_PATH_SEC3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_RX_PATH_SEC4)] = RD_WR_REG,
[WCD939X_REG(WCD939X_RX_PATH_SEC5)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL4)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL5)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL6)] = RD_REG,
[WCD939X_REG(WCD939X_CTL7)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL8)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL9)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL10)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL11)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL12)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL13)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL14)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL15)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL16)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL17)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL18)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CTL19)] = RD_WR_REG,
[WCD939X_REG(WCD939X_R_CTL0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_R_CTL1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_R_CTL2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_R_CTL3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_R_CTL4)] = RD_WR_REG,
[WCD939X_REG(WCD939X_R_CTL5)] = RD_WR_REG,
[WCD939X_REG(WCD939X_R_CTL6)] = RD_REG,
[WCD939X_REG(WCD939X_R_CTL7)] = RD_WR_REG,
[WCD939X_REG(WCD939X_R_CTL8)] = RD_WR_REG,
[WCD939X_REG(WCD939X_R_CTL9)] = RD_WR_REG,
[WCD939X_REG(WCD939X_R_CTL10)] = RD_WR_REG,
[WCD939X_REG(WCD939X_R_CTL11)] = RD_WR_REG,
[WCD939X_REG(WCD939X_R_CTL12)] = RD_WR_REG,
[WCD939X_REG(WCD939X_R_CTL13)] = RD_WR_REG,
[WCD939X_REG(WCD939X_R_CTL14)] = RD_WR_REG,
[WCD939X_REG(WCD939X_R_CTL15)] = RD_WR_REG,
[WCD939X_REG(WCD939X_R_CTL16)] = RD_WR_REG,
[WCD939X_REG(WCD939X_R_CTL17)] = RD_WR_REG,
[WCD939X_REG(WCD939X_R_CTL18)] = RD_WR_REG,
[WCD939X_REG(WCD939X_R_CTL19)] = RD_WR_REG,
[WCD939X_REG(WCD939X_PATH_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CFG0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CFG1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CFG2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CFG3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSD_HPHL_PATH_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSD_HPHL_CFG0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSD_HPHL_CFG1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSD_HPHL_CFG2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSD_HPHL_CFG3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CFG4)] = RD_WR_REG,
[WCD939X_REG(WCD939X_CFG5)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSD_HPHR_PATH_CTL)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSD_HPHR_CFG0)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSD_HPHR_CFG1)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSD_HPHR_CFG2)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSD_HPHR_CFG3)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSD_HPHR_CFG4)] = RD_WR_REG,
[WCD939X_REG(WCD939X_DSD_HPHR_CFG5)] = RD_WR_REG,
};

4494
asoc/codecs/wcd939x/wcd939x.c Normal file
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File diff suppressed because it is too large Load Diff

138
asoc/codecs/wcd939x/wcd939x.h Normal file
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@@ -0,0 +1,138 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _WCD939X_H
#define _WCD939X_H
#include <bindings/audio-codec-port-types.h>
#define WCD939X_MAX_SLAVE_CH_TYPES 13
#define ZERO 0
#define WCD939X_DRV_NAME "wcd939x_codec"
enum {
WCD9390 = 0,
WCD9395 = 5,
};
/* from WCD to SWR DMIC events */
enum {
WCD939X_EVT_SSR_DOWN,
WCD939X_EVT_SSR_UP,
};
struct swr_slave_ch_map {
u8 ch_type;
u8 index;
};
static const struct swr_slave_ch_map swr_slv_tx_ch_idx[] = {
{ADC1, 0},
{ADC2, 1},
{ADC3, 2},
{ADC4, 3},
{DMIC0, 4},
{DMIC1, 5},
{MBHC, 6},
{DMIC2, 6},
{DMIC3, 7},
{DMIC4, 8},
{DMIC5, 9},
{DMIC6, 10},
{DMIC7, 11},
};
static int swr_master_ch_map[] = {
ZERO,
SWRM_TX_PCM_OUT,
SWRM_TX1_CH1,
SWRM_TX1_CH2,
SWRM_TX1_CH3,
SWRM_TX1_CH4,
SWRM_TX2_CH1,
SWRM_TX2_CH2,
SWRM_TX2_CH3,
SWRM_TX2_CH4,
SWRM_TX3_CH1,
SWRM_TX3_CH2,
SWRM_TX3_CH3,
SWRM_TX3_CH4,
SWRM_TX_PCM_IN,
};
#if IS_ENABLED(CONFIG_SND_SOC_WCD939X)
int wcd939x_info_create_codec_entry(struct snd_info_entry *codec_root,
struct snd_soc_component *component);
int wcd939x_get_codec_variant(struct snd_soc_component *component);
int wcd939x_codec_force_enable_micbias_v2(struct snd_soc_component *wcd939x,
int event, int micb_num);
int wcd939x_swr_dmic_register_notifier(struct snd_soc_component *wcd939x,
struct notifier_block *nblock,
bool enable);
int wcd939x_codec_get_dev_num(struct snd_soc_component *component);
static inline int wcd939x_slave_get_master_ch_val(int ch)
{
int i;
for (i = 0; i < WCD939X_MAX_SLAVE_CH_TYPES; i++)
if (ch == swr_master_ch_map[i])
return i;
return 0;
}
static inline int wcd939x_slave_get_master_ch(int idx)
{
return swr_master_ch_map[idx];
}
static inline int wcd939x_slave_get_slave_ch_val(int ch)
{
int i;
for (i = 0; i < WCD939X_MAX_SLAVE_CH_TYPES; i++)
if (ch == swr_slv_tx_ch_idx[i].ch_type)
return swr_slv_tx_ch_idx[i].index;
return -EINVAL;
}
#else
static inline int wcd939x_info_create_codec_entry(
struct snd_info_entry *codec_root,
struct snd_soc_component *component)
{
return 0;
}
static inline int wcd939x_get_codec_variant(struct snd_soc_component *component)
{
return 0;
}
static inline int wcd939x_codec_force_enable_micbias_v2(
struct snd_soc_component *wcd939x,
int event, int micb_num)
{
return 0;
}
static inline int wcd939x_slave_get_master_ch_val(int ch)
{
return 0;
}
static inline int wcd939x_slave_get_master_ch(int idx)
{
return 0;
}
static inline int wcd939x_slave_get_slave_ch_val(int ch)
{
return 0;
}
static int wcd939x_codec_get_dev_num(struct snd_soc_component *component)
{
return 0;
}
#endif /* CONFIG_SND_SOC_WCD939X */
#endif /* _WCD939X_H */