disp: msm: dsi: fix pll lane count in split link usecase

In split link usecase with single DSI and dual sublink, the
pixel clock rate should  be calculated based on effective lanes
rather than cumulative lanes on that DSI PHY. This effective lanes
can be expressed as number of lanes being used per sublink.

Change-Id: Ia534e816cc64b62c5fe0b9fcaabb9ba52d05bab0
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>

msm/dsi/dsi_defs.h

@@ -771,23 +771,6 @@ static inline int dsi_pixel_format_to_bpp(enum dsi_pixel_format fmt)
 	return 24;
 }
 
-/* return number of DSI data lanes */
-static inline int dsi_get_num_of_data_lanes(enum dsi_data_lanes dlanes)
-{
-	int num_of_lanes = 0;
-
-	if (dlanes & DSI_DATA_LANE_0)
-		num_of_lanes++;
-	if (dlanes & DSI_DATA_LANE_1)
-		num_of_lanes++;
-	if (dlanes & DSI_DATA_LANE_2)
-		num_of_lanes++;
-	if (dlanes & DSI_DATA_LANE_3)
-		num_of_lanes++;
-
-	return num_of_lanes;
-}
-
 static inline u64 dsi_h_active_dce(struct dsi_mode_info *mode)
 {
 	u64 h_active = 0;