From 213d49059349bcfc98e3436e3601b5197a52b8de Mon Sep 17 00:00:00 2001 From: Shashank Babu Chinta Venkata Date: Wed, 27 Oct 2021 00:11:05 -0700 Subject: [PATCH] disp: msm: dsi: fix pll lane count in split link usecase In split link usecase with single DSI and dual sublink, the pixel clock rate should be calculated based on effective lanes rather than cumulative lanes on that DSI PHY. This effective lanes can be expressed as number of lanes being used per sublink. Change-Id: Ia534e816cc64b62c5fe0b9fcaabb9ba52d05bab0 Signed-off-by: Shashank Babu Chinta Venkata --- msm/dsi/dsi_defs.h | 17 ----------------- msm/dsi/dsi_phy.c | 37 ++++++++++++++++++++++++++++++++++++- 2 files changed, 36 insertions(+), 18 deletions(-) diff --git a/msm/dsi/dsi_defs.h b/msm/dsi/dsi_defs.h index 11074df7f5..4ab7abee9a 100644 --- a/msm/dsi/dsi_defs.h +++ b/msm/dsi/dsi_defs.h @@ -771,23 +771,6 @@ static inline int dsi_pixel_format_to_bpp(enum dsi_pixel_format fmt) return 24; } -/* return number of DSI data lanes */ -static inline int dsi_get_num_of_data_lanes(enum dsi_data_lanes dlanes) -{ - int num_of_lanes = 0; - - if (dlanes & DSI_DATA_LANE_0) - num_of_lanes++; - if (dlanes & DSI_DATA_LANE_1) - num_of_lanes++; - if (dlanes & DSI_DATA_LANE_2) - num_of_lanes++; - if (dlanes & DSI_DATA_LANE_3) - num_of_lanes++; - - return num_of_lanes; -} - static inline u64 dsi_h_active_dce(struct dsi_mode_info *mode) { u64 h_active = 0; diff --git a/msm/dsi/dsi_phy.c b/msm/dsi/dsi_phy.c index 2305790fee..a6160a24a3 100644 --- a/msm/dsi/dsi_phy.c +++ b/msm/dsi/dsi_phy.c @@ -764,6 +764,40 @@ error: return rc; } +/** + * dsi_phy_get_data_lanes_count() - Count the data lines need to be configured + * @dsi_phy: DSI PHY handle. + * + * Return: Count of data lanes being used + */ +static inline int dsi_phy_get_data_lanes_count(struct msm_dsi_phy *phy) +{ + int num_of_lanes = 0; + enum dsi_data_lanes dlanes; + + dlanes = phy->data_lanes; + + /** + * For split link use case effective data lines need to be used + * rather than total lanes on PHY for clock calculation and hence we + * fall back pll->lanes to lanes_per_sublink rather than total + * lanes. + */ + if (phy->cfg.split_link.enabled) + return phy->cfg.split_link.lanes_per_sublink; + + if (dlanes & DSI_DATA_LANE_0) + num_of_lanes++; + if (dlanes & DSI_DATA_LANE_1) + num_of_lanes++; + if (dlanes & DSI_DATA_LANE_2) + num_of_lanes++; + if (dlanes & DSI_DATA_LANE_3) + num_of_lanes++; + + return num_of_lanes; +} + /** * dsi_phy_configure() - Configure DSI PHY PLL * @dsi_phy: DSI PHY handle. @@ -779,7 +813,8 @@ int dsi_phy_configure(struct msm_dsi_phy *phy, bool commit) phy->pll->type = phy->cfg.phy_type; phy->pll->bpp = dsi_pixel_format_to_bpp(phy->dst_format); - phy->pll->lanes = dsi_get_num_of_data_lanes(phy->data_lanes); + phy->pll->lanes = dsi_phy_get_data_lanes_count(phy); + if (phy->hw.ops.configure) rc = phy->hw.ops.configure(phy->pll, commit);