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Merge "soc: swr: update interval high register"

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This commit is contained in:
qctecmdr
2020-07-17 22:40:14 -07:00
committed by Gerrit - the friendly Code Review server
parent d70f2387d0 96262c74ed
commit 1b7dc59d11
2 changed files with 9 additions and 1 deletions
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8
soc/swr-mstr-ctrl.c
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@@ -1275,10 +1275,16 @@ static void swrm_copy_data_port_config(struct swr_master *master, u8 bank)
bank)); bank));
reg[len] = SWRM_CMD_FIFO_WR_CMD; reg[len] = SWRM_CMD_FIFO_WR_CMD;
val[len++] = SWR_REG_VAL_PACK(mport->sinterval, val[len++] = SWR_REG_VAL_PACK(mport->sinterval & 0xFF,
port_req->dev_num, 0x00, port_req->dev_num, 0x00,
SWRS_DP_SAMPLE_CONTROL_1_BANK(slv_id, SWRS_DP_SAMPLE_CONTROL_1_BANK(slv_id,
bank)); bank));
reg[len] = SWRM_CMD_FIFO_WR_CMD;
val[len++] = SWR_REG_VAL_PACK((mport->sinterval >> 8)& 0xFF,
port_req->dev_num, 0x00,
SWRS_DP_SAMPLE_CONTROL_2_BANK(slv_id,
bank));
/* Assumption: If different channels in the same port /* Assumption: If different channels in the same port
* on master is enabled for different slaves, then each * on master is enabled for different slaves, then each
* slave offset should be configured differently. * slave offset should be configured differently.

2
soc/swrm_registers.h
View File

@@ -232,6 +232,8 @@
SWRS_DP_REG_OFFSET(n, m)) SWRS_DP_REG_OFFSET(n, m))
#define SWRS_DP_SAMPLE_CONTROL_1_BANK(n, m) (SWRS_BASE_ADDRESS + 0x122 + \ #define SWRS_DP_SAMPLE_CONTROL_1_BANK(n, m) (SWRS_BASE_ADDRESS + 0x122 + \
SWRS_DP_REG_OFFSET(n, m)) SWRS_DP_REG_OFFSET(n, m))
#define SWRS_DP_SAMPLE_CONTROL_2_BANK(n, m) (SWRS_BASE_ADDRESS + 0x123 + \
SWRS_DP_REG_OFFSET(n, m))
#define SWRS_DP_OFFSET_CONTROL_1_BANK(n, m) (SWRS_BASE_ADDRESS + 0x124 + \ #define SWRS_DP_OFFSET_CONTROL_1_BANK(n, m) (SWRS_BASE_ADDRESS + 0x124 + \
SWRS_DP_REG_OFFSET(n, m)) SWRS_DP_REG_OFFSET(n, m))
#define SWRS_DP_OFFSET_CONTROL_2_BANK(n, m) (SWRS_BASE_ADDRESS + 0x125 + \ #define SWRS_DP_OFFSET_CONTROL_2_BANK(n, m) (SWRS_BASE_ADDRESS + 0x125 + \