samsung-sm8650/android_kernel_samsung_sm8650-modules
1
0
Förgrening 0
Kod Ärenden Pull-förfrågningar Actions Packages Projekt Släpp Wiki Aktiviteter

qcacmn: Data path changes for big endian platform

Bläddra i källkod 
Add reo ring descrptor swap in case of big endian platform.
Convert msi_data into little endian format before writing into
MSI_DATA register. Also change into little endian format while accessing
the shared LMAC registers.

Change-Id: I07f4ae4e6df4608201b63d325c2cbc37436d1592
This commit is contained in:
Nandha Kishore Easwaran
2020-10-20 12:58:35 +05:30
committad av snandini
förälder 47c1479e3f
incheckning 1a0bc1efc4
4 ändrade filer med 35 tillägg och 10 borttagningar
Download Patch File Download Diff File Expand all files Collapse all files

25
hal/wifi3.0/hal_generic_api.h
Visa fil

@@ -1642,6 +1642,22 @@ hal_rx_status_get_tlv_info_generic(void *rx_tlv_hdr, void *ppduinfo,
return HAL_TLV_STATUS_PPDU_NOT_DONE;
}
static void hal_setup_reo_swap(struct hal_soc *soc)
{
uint32_t reg_val;
reg_val = HAL_REG_READ(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(
SEQ_WCSS_UMAC_REO_REG_OFFSET));
reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, WRITE_STRUCT_SWAP, 1);
reg_val |= HAL_SM(HWIO_REO_R0_CACHE_CTL_CONFIG, READ_STRUCT_SWAP, 1);
#if defined(QDF_BIG_ENDIAN_MACHINE)
HAL_REG_WRITE(soc, HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(
SEQ_WCSS_UMAC_REO_REG_OFFSET), reg_val);
#endif
}
/**
* hal_reo_setup - Initialize HW REO block
*
@@ -1666,6 +1682,9 @@ static void hal_reo_setup_generic(struct hal_soc *soc,
* Default setting is to send all errors to release ring.
*/
/* Set the reo descriptor swap bits in case of BIG endian platform */
hal_setup_reo_swap(soc);
HAL_REG_WRITE(soc,
HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
SEQ_WCSS_UMAC_REO_REG_OFFSET),
@@ -1813,7 +1832,8 @@ void hal_srng_src_hw_init_generic(struct hal_soc *hal,
SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB,
MSI1_ENABLE), 1);
SRNG_SRC_REG_WRITE(srng, MSI1_BASE_MSB, reg_val);
SRNG_SRC_REG_WRITE(srng, MSI1_DATA, srng->msi_data);
SRNG_SRC_REG_WRITE(srng, MSI1_DATA,
qdf_cpu_to_le32(srng->msi_data));
}
SRNG_SRC_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff);
@@ -1928,7 +1948,8 @@ void hal_srng_dst_hw_init_generic(struct hal_soc *hal,
SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB,
MSI1_ENABLE), 1);
SRNG_DST_REG_WRITE(srng, MSI1_BASE_MSB, reg_val);
SRNG_DST_REG_WRITE(srng, MSI1_DATA, srng->msi_data);
SRNG_DST_REG_WRITE(srng, MSI1_DATA,
qdf_cpu_to_le32(srng->msi_data));
}
SRNG_DST_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff);