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cnss2: Avoid PBL/SBL region dump in Mission mode

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Access to PBL and SBL log region in SRAM is restricted in
Mission mode. Avoid PBL/SBL log region dump in Mission mode.

Change-Id: Ia8813ccd9e2c0339c280e6cb6d6f0bab0bee206e
CRs-Fixed: 3432159
This commit is contained in:
Naman Padhiar
2023-03-31 15:26:34 +05:30
committed by Madan Koyyalamudi
parent 3ef55a9a08
commit 190e1efaa9
2 changed files with 17 additions and 0 deletions
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13
cnss2/pci.c
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@@ -1611,6 +1611,7 @@ EXPORT_SYMBOL(cnss_get_pci_slot);
*/ */
static void cnss_pci_dump_bl_sram_mem(struct cnss_pci_data *pci_priv) static void cnss_pci_dump_bl_sram_mem(struct cnss_pci_data *pci_priv)
{ {
enum mhi_ee_type ee;
u32 mem_addr, val, pbl_log_max_size, sbl_log_max_size; u32 mem_addr, val, pbl_log_max_size, sbl_log_max_size;
u32 pbl_log_sram_start; u32 pbl_log_sram_start;
u32 pbl_stage, sbl_log_start, sbl_log_size; u32 pbl_stage, sbl_log_start, sbl_log_size;
@@ -1667,6 +1668,12 @@ static void cnss_pci_dump_bl_sram_mem(struct cnss_pci_data *pci_priv)
cnss_pr_dbg("PBL_WLAN_BOOT_CFG: 0x%08x PBL_BOOTSTRAP_STATUS: 0x%08x\n", cnss_pr_dbg("PBL_WLAN_BOOT_CFG: 0x%08x PBL_BOOTSTRAP_STATUS: 0x%08x\n",
pbl_wlan_boot_cfg, pbl_bootstrap_status); pbl_wlan_boot_cfg, pbl_bootstrap_status);
ee = mhi_get_exec_env(pci_priv->mhi_ctrl);
if (CNSS_MHI_IN_MISSION_MODE(ee)) {
cnss_pr_dbg("Avoid Dumping PBL log data in Mission mode\n");
return;
}
cnss_pr_dbg("Dumping PBL log data\n"); cnss_pr_dbg("Dumping PBL log data\n");
for (i = 0; i < pbl_log_max_size; i += sizeof(val)) { for (i = 0; i < pbl_log_max_size; i += sizeof(val)) {
mem_addr = pbl_log_sram_start + i; mem_addr = pbl_log_sram_start + i;
@@ -1684,6 +1691,12 @@ static void cnss_pci_dump_bl_sram_mem(struct cnss_pci_data *pci_priv)
return; return;
} }
ee = mhi_get_exec_env(pci_priv->mhi_ctrl);
if (CNSS_MHI_IN_MISSION_MODE(ee)) {
cnss_pr_dbg("Avoid Dumping SBL log data in Mission mode\n");
return;
}
cnss_pr_dbg("Dumping SBL log data\n"); cnss_pr_dbg("Dumping SBL log data\n");
for (i = 0; i < sbl_log_size; i += sizeof(val)) { for (i = 0; i < sbl_log_size; i += sizeof(val)) {
mem_addr = sbl_log_start + i; mem_addr = sbl_log_start + i;

4
cnss2/pci.h
View File

@@ -33,6 +33,10 @@
#define LINK_TRAINING_RETRY_DELAY_MS 500 #define LINK_TRAINING_RETRY_DELAY_MS 500
#define MSI_USERS 4 #define MSI_USERS 4
#define CNSS_MHI_IN_MISSION_MODE(ee) (ee == MHI_EE_AMSS || \
ee == MHI_EE_WFW || \
ee == MHI_EE_FP)
enum cnss_mhi_state { enum cnss_mhi_state {
CNSS_MHI_INIT, CNSS_MHI_INIT,
CNSS_MHI_DEINIT, CNSS_MHI_DEINIT,