asoc: Add support for 11P2896MHz RX clk config

1. Update RX CLK config for 11P2896MHz.
2. Add condition to update Droop sel coeffs for 11P28MHz
   and 9P6MHz RX CLK.
3. Upate SWR port config for 44.1Khz sample rate usecase.
4. Unselect RX_TOP.SWR_CTRL(0x6AC0008) for RX CLK 11P28MHz.
5. Update HD2_CTL L/R registers as per latest seq version.

Change-Id: Ifac2c03e3d1bf522fe2a4d942341d9071a1e6239
Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>

asoc/codecs/lpass-cdc/internal.h

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _LPASS_CDC_INTERNAL_H
@@ -17,6 +18,7 @@ enum {
 	LPASS_CDC_WCD_EVT_SSR_UP,
 	LPASS_CDC_WCD_EVT_PA_ON_POST_FSCLK,
 	LPASS_CDC_WCD_EVT_PA_ON_POST_FSCLK_ADIE_LB,
+	LPASS_CDC_WCD_EVT_CLK_NOTIFY,
 };
 
 enum {