17a7fb3f4d
1. Update RX CLK config for 11P2896MHz. 2. Add condition to update Droop sel coeffs for 11P28MHz and 9P6MHz RX CLK. 3. Upate SWR port config for 44.1Khz sample rate usecase. 4. Unselect RX_TOP.SWR_CTRL(0x6AC0008) for RX CLK 11P28MHz. 5. Update HD2_CTL L/R registers as per latest seq version. Change-Id: Ifac2c03e3d1bf522fe2a4d942341d9071a1e6239 Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
111 lines
3.0 KiB
C
111 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _LPASS_CDC_INTERNAL_H
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#define _LPASS_CDC_INTERNAL_H
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#include "lpass-cdc-registers.h"
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#define LPASS_CDC_CHILD_DEVICES_MAX 6
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/* from lpass_cdc to WCD events */
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enum {
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LPASS_CDC_WCD_EVT_TX_CH_HOLD_CLEAR = 1,
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LPASS_CDC_WCD_EVT_PA_OFF_PRE_SSR,
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LPASS_CDC_WCD_EVT_SSR_DOWN,
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LPASS_CDC_WCD_EVT_SSR_UP,
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LPASS_CDC_WCD_EVT_PA_ON_POST_FSCLK,
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LPASS_CDC_WCD_EVT_PA_ON_POST_FSCLK_ADIE_LB,
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LPASS_CDC_WCD_EVT_CLK_NOTIFY,
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};
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enum {
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REG_NO_ACCESS,
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RD_REG,
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WR_REG,
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RD_WR_REG
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};
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/* from WCD to lpass_cdc events */
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enum {
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WCD_LPASS_CDC_EVT_RX_MUTE = 1, /* for RX mute/unmute */
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WCD_LPASS_CDC_EVT_IMPED_TRUE, /* for imped true */
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WCD_LPASS_CDC_EVT_IMPED_FALSE, /* for imped false */
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WCD_LPASS_CDC_EVT_RX_COMPANDER_SOFT_RST,
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WCD_LPASS_CDC_EVT_BCS_CLK_OFF,
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WCD_LPASS_CDC_EVT_RX_PA_GAIN_UPDATE,
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WCD_LPASS_CDC_EVT_HPHL_HD2_ENABLE, /* to enable hd2 config for hphl */
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WCD_LPASS_CDC_EVT_HPHR_HD2_ENABLE, /* to enable hd2 config for hphr */
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};
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struct wcd_ctrl_platform_data {
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void *handle;
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int (*update_wcd_event)(void *handle, u16 event, u32 data);
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int (*register_notifier)(void *handle,
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struct notifier_block *nblock,
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bool enable);
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};
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struct lpass_cdc_priv {
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struct device *dev;
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struct snd_soc_component *component;
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struct regmap *regmap;
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struct mutex io_lock;
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struct mutex clk_lock;
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struct mutex vote_lock;
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bool va_without_decimation;
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bool macros_supported[MAX_MACRO];
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bool dev_up;
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bool pre_dev_up;
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bool initial_boot;
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struct macro_ops macro_params[MAX_MACRO];
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struct snd_soc_dai_driver *lpass_cdc_dais;
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u16 num_dais;
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u16 num_macros_registered;
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u16 num_macros;
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u16 current_mclk_mux_macro[MAX_MACRO];
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struct work_struct lpass_cdc_add_child_devices_work;
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u32 version;
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struct clk *lpass_core_hw_vote;
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struct clk *lpass_audio_hw_vote;
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int core_hw_vote_count;
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int core_audio_vote_count;
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/* Entry for version info */
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struct snd_info_entry *entry;
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struct snd_info_entry *version_entry;
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int (*read_dev)(struct lpass_cdc_priv *priv,
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u16 macro_id, u16 reg, u8 *val);
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int (*write_dev)(struct lpass_cdc_priv *priv,
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u16 macro_id, u16 reg, u8 val);
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struct platform_device *pdev_child_devices
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[LPASS_CDC_CHILD_DEVICES_MAX];
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u16 child_count;
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struct wcd_ctrl_platform_data plat_data;
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struct device *wcd_dev;
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struct blocking_notifier_head notifier;
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struct device *clk_dev;
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rsc_clk_cb_t rsc_clk_cb;
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s32 dmic_0_1_clk_cnt;
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s32 dmic_2_3_clk_cnt;
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s32 dmic_4_5_clk_cnt;
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s32 dmic_6_7_clk_cnt;
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u8 dmic_0_1_clk_div;
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u8 dmic_2_3_clk_div;
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u8 dmic_4_5_clk_div;
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u8 dmic_6_7_clk_div;
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};
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struct regmap *lpass_cdc_regmap_init(struct device *dev,
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const struct regmap_config *config);
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int lpass_cdc_get_macro_id(bool va_no_dec_flag, u16 reg);
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extern const struct regmap_config lpass_cdc_regmap_config;
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extern u8 *lpass_cdc_reg_access[MAX_MACRO];
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extern const u16 macro_id_base_offset[MAX_MACRO];
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#endif
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