qcacmn: Hal related changes for QCA5332
1. Changes to move hal_tx_config_rbm_mapping_be function from common to device specific as it has ppe related snippets. 2. Changes to remove all PPE related codes in QCA5332 hal code. 3. Changes to correct macros according to fw_hrs. 4. Changes to move functions with device specific Macros to header files so that it gets compiled with respective device's FW headers and gets correct Macros Change-Id: I479b406f318aa42d2b1032349aaf42d95b8c18e5 CRs-Fixed: 3235966
This commit is contained in:
Hariharan Ramanathan
committed by
Madan Koyyalamudi
Madan Koyyalamudi
parent
7e799fcbae
commit
16630d2422
@@ -2737,4 +2737,456 @@ static void hal_reo_shared_qaddr_detach_be(hal_soc_handle_t hal_soc_hdl)
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hal->reo_qref.non_mlo_reo_qref_table_paddr, 0);
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}
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#endif
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/**
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* hal_tx_vdev_mismatch_routing_set - set vdev mismatch exception routing
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* @hal_soc: HAL SoC context
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* @config: HAL_TX_VDEV_MISMATCH_TQM_NOTIFY - route via TQM
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* HAL_TX_VDEV_MISMATCH_FW_NOTIFY - route via FW
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*
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* Return: void
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*/
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#ifdef HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK
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static inline void
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hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl,
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enum hal_tx_vdev_mismatch_notify
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config)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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uint32_t reg_addr, reg_val = 0;
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uint32_t val = 0;
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reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE);
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val = HAL_REG_READ(hal_soc, reg_addr);
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/* reset the corresponding bits in register */
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val &= (~(HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK));
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/* set config value */
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reg_val = val | (config <<
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HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_SHFT);
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HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
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}
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#else
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static inline void
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hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl,
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enum hal_tx_vdev_mismatch_notify
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config)
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{
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}
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#endif
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/**
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* hal_tx_mcast_mlo_reinject_routing_set - set MLO multicast reinject routing
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* @hal_soc: HAL SoC context
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* @config: HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY - route via FW
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* HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY - route via TQM
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*
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* Return: void
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*/
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#if defined(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK) && \
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defined(WLAN_MCAST_MLO)
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static inline void
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hal_tx_mcast_mlo_reinject_routing_set_generic_be(
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hal_soc_handle_t hal_soc_hdl,
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enum hal_tx_mcast_mlo_reinject_notify config)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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uint32_t reg_addr, reg_val = 0;
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uint32_t val = 0;
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reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE);
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val = HAL_REG_READ(hal_soc, reg_addr);
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/* reset the corresponding bits in register */
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val &= (~(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK));
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/* set config value */
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reg_val = val | (config << HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_SHFT);
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HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
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}
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#else
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static inline void
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hal_tx_mcast_mlo_reinject_routing_set_generic_be(
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hal_soc_handle_t hal_soc_hdl,
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enum hal_tx_mcast_mlo_reinject_notify config)
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{
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}
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#endif
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/**
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* hal_get_ba_aging_timeout_be - Get BA Aging timeout
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*
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* @hal_soc: Opaque HAL SOC handle
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* @ac: Access category
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* @value: window size to get
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*/
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static inline
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void hal_get_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl,
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uint8_t ac, uint32_t *value)
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{
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struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
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switch (ac) {
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case WME_AC_BE:
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*value = HAL_REG_READ(soc,
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HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
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REO_REG_REG_BASE)) / 1000;
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break;
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case WME_AC_BK:
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*value = HAL_REG_READ(soc,
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HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
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REO_REG_REG_BASE)) / 1000;
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break;
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case WME_AC_VI:
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*value = HAL_REG_READ(soc,
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HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
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REO_REG_REG_BASE)) / 1000;
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break;
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case WME_AC_VO:
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*value = HAL_REG_READ(soc,
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HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
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REO_REG_REG_BASE)) / 1000;
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break;
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default:
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QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
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"Invalid AC: %d\n", ac);
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}
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}
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/**
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* hal_setup_link_idle_list_generic_be - Setup scattered idle list using the
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* buffer list provided
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*
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* @hal_soc: Opaque HAL SOC handle
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* @scatter_bufs_base_paddr: Array of physical base addresses
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* @scatter_bufs_base_vaddr: Array of virtual base addresses
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* @num_scatter_bufs: Number of scatter buffers in the above lists
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* @scatter_buf_size: Size of each scatter buffer
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* @last_buf_end_offset: Offset to the last entry
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* @num_entries: Total entries of all scatter bufs
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*
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* Return: None
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*/
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static inline void
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hal_setup_link_idle_list_generic_be(struct hal_soc *soc,
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qdf_dma_addr_t scatter_bufs_base_paddr[],
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void *scatter_bufs_base_vaddr[],
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uint32_t num_scatter_bufs,
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uint32_t scatter_buf_size,
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uint32_t last_buf_end_offset,
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uint32_t num_entries)
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{
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int i;
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uint32_t *prev_buf_link_ptr = NULL;
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uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size;
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uint32_t val;
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/* Link the scatter buffers */
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for (i = 0; i < num_scatter_bufs; i++) {
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if (i > 0) {
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prev_buf_link_ptr[0] =
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scatter_bufs_base_paddr[i] & 0xffffffff;
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prev_buf_link_ptr[1] = HAL_SM(
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HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
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BASE_ADDRESS_39_32,
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((uint64_t)(scatter_bufs_base_paddr[i])
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>> 32)) | HAL_SM(
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HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
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ADDRESS_MATCH_TAG,
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ADDRESS_MATCH_TAG_VAL);
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}
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prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] +
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scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE);
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}
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/* TBD: Register programming partly based on MLD & the rest based on
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* inputs from HW team. Not complete yet.
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*/
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reg_scatter_buf_size = (scatter_buf_size -
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WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) / 64;
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reg_tot_scatter_buf_size = ((scatter_buf_size -
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WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs) / 64;
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(
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WBM_REG_REG_BASE),
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HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, SCATTER_BUFFER_SIZE,
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reg_scatter_buf_size) |
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HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, LINK_DESC_IDLE_LIST_MODE,
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0x1));
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(
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WBM_REG_REG_BASE),
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HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE,
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SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST,
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reg_tot_scatter_buf_size));
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(
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WBM_REG_REG_BASE),
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scatter_bufs_base_paddr[0] & 0xffffffff);
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(
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WBM_REG_REG_BASE),
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((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) &
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HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK);
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(
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WBM_REG_REG_BASE),
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HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
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BASE_ADDRESS_39_32, ((uint64_t)(scatter_bufs_base_paddr[0])
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>> 32)) |
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HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
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ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL));
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/* ADDRESS_MATCH_TAG field in the above register is expected to match
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* with the upper bits of link pointer. The above write sets this field
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* to zero and we are also setting the upper bits of link pointers to
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* zero while setting up the link list of scatter buffers above
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*/
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/* Setup head and tail pointers for the idle list */
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(
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WBM_REG_REG_BASE),
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scatter_bufs_base_paddr[num_scatter_bufs - 1] & 0xffffffff);
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(
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WBM_REG_REG_BASE),
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HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
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BUFFER_ADDRESS_39_32,
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((uint64_t)(scatter_bufs_base_paddr[num_scatter_bufs - 1])
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>> 32)) |
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HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
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HEAD_POINTER_OFFSET, last_buf_end_offset >> 2));
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(
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WBM_REG_REG_BASE),
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scatter_bufs_base_paddr[0] & 0xffffffff);
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(
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WBM_REG_REG_BASE),
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scatter_bufs_base_paddr[0] & 0xffffffff);
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(
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WBM_REG_REG_BASE),
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HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
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BUFFER_ADDRESS_39_32,
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((uint64_t)(scatter_bufs_base_paddr[0]) >>
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32)) | HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
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TAIL_POINTER_OFFSET, 0));
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(
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WBM_REG_REG_BASE),
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2 * num_entries);
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/* Set RING_ID_DISABLE */
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val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1);
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/*
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* SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence
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* check the presence of the bit before toggling it.
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*/
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#ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK
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val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1);
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#endif
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(WBM_REG_REG_BASE),
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val);
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}
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#ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
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#define HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15 0x8000
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#endif
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/**
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* hal_cookie_conversion_reg_cfg_generic_be() - set cookie conversion relevant register
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* for REO/WBM
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* @soc: HAL soc handle
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* @cc_cfg: structure pointer for HW cookie conversion configuration
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*
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* Return: None
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*/
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static inline
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void hal_cookie_conversion_reg_cfg_generic_be(hal_soc_handle_t hal_soc_hdl,
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struct hal_hw_cc_config *cc_cfg)
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{
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uint32_t reg_addr, reg_val = 0;
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struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
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/* REO CFG */
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reg_addr = HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(REO_REG_REG_BASE);
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reg_val = cc_cfg->lut_base_addr_31_0;
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HAL_REG_WRITE(soc, reg_addr, reg_val);
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reg_addr = HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(REO_REG_REG_BASE);
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reg_val = 0;
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reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
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SW_COOKIE_CONVERT_GLOBAL_ENABLE,
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cc_cfg->cc_global_en);
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reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
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SW_COOKIE_CONVERT_ENABLE,
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cc_cfg->cc_global_en);
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reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
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PAGE_ALIGNMENT,
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cc_cfg->page_4k_align);
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reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
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COOKIE_OFFSET_MSB,
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cc_cfg->cookie_offset_msb);
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reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
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COOKIE_PAGE_MSB,
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cc_cfg->cookie_page_msb);
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reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
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CMEM_LUT_BASE_ADDR_39_32,
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cc_cfg->lut_base_addr_39_32);
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HAL_REG_WRITE(soc, reg_addr, reg_val);
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/* WBM CFG */
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reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(WBM_REG_REG_BASE);
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reg_val = cc_cfg->lut_base_addr_31_0;
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HAL_REG_WRITE(soc, reg_addr, reg_val);
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reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(WBM_REG_REG_BASE);
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reg_val = 0;
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
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PAGE_ALIGNMENT,
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cc_cfg->page_4k_align);
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
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COOKIE_OFFSET_MSB,
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cc_cfg->cookie_offset_msb);
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
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COOKIE_PAGE_MSB,
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cc_cfg->cookie_page_msb);
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
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CMEM_LUT_BASE_ADDR_39_32,
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cc_cfg->lut_base_addr_39_32);
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HAL_REG_WRITE(soc, reg_addr, reg_val);
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/*
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* WCSS_UMAC_WBM_R0_SW_COOKIE_CONVERT_CFG default value is 0x1FE,
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*/
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reg_addr = HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(WBM_REG_REG_BASE);
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reg_val = 0;
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
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WBM_COOKIE_CONV_GLOBAL_ENABLE,
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cc_cfg->cc_global_en);
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
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WBM2SW6_COOKIE_CONVERSION_EN,
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cc_cfg->wbm2sw6_cc_en);
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
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WBM2SW5_COOKIE_CONVERSION_EN,
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cc_cfg->wbm2sw5_cc_en);
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
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WBM2SW4_COOKIE_CONVERSION_EN,
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cc_cfg->wbm2sw4_cc_en);
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
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WBM2SW3_COOKIE_CONVERSION_EN,
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cc_cfg->wbm2sw3_cc_en);
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
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WBM2SW2_COOKIE_CONVERSION_EN,
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cc_cfg->wbm2sw2_cc_en);
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
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WBM2SW1_COOKIE_CONVERSION_EN,
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cc_cfg->wbm2sw1_cc_en);
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
|
||||
WBM2SW0_COOKIE_CONVERSION_EN,
|
||||
cc_cfg->wbm2sw0_cc_en);
|
||||
reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
|
||||
WBM2FW_COOKIE_CONVERSION_EN,
|
||||
cc_cfg->wbm2fw_cc_en);
|
||||
HAL_REG_WRITE(soc, reg_addr, reg_val);
|
||||
|
||||
#ifdef HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK
|
||||
reg_addr = HWIO_WBM_R0_WBM_CFG_2_ADDR(WBM_REG_REG_BASE);
|
||||
reg_val = 0;
|
||||
reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
|
||||
COOKIE_DEBUG_SEL,
|
||||
cc_cfg->cc_global_en);
|
||||
|
||||
reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
|
||||
COOKIE_CONV_INDICATION_EN,
|
||||
cc_cfg->cc_global_en);
|
||||
|
||||
reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
|
||||
ERROR_PATH_COOKIE_CONV_EN,
|
||||
cc_cfg->error_path_cookie_conv_en);
|
||||
|
||||
reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
|
||||
RELEASE_PATH_COOKIE_CONV_EN,
|
||||
cc_cfg->release_path_cookie_conv_en);
|
||||
|
||||
HAL_REG_WRITE(soc, reg_addr, reg_val);
|
||||
#endif
|
||||
#ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
|
||||
/*
|
||||
* To enable indication for HW cookie conversion done or not for
|
||||
* WBM, WCSS_UMAC_WBM_R0_MISC_CONTROL spare_control field 15th
|
||||
* bit spare_control[15] should be set.
|
||||
*/
|
||||
reg_addr = HWIO_WBM_R0_MISC_CONTROL_ADDR(WBM_REG_REG_BASE);
|
||||
reg_val = HAL_REG_READ(soc, reg_addr);
|
||||
reg_val |= HAL_SM(HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL,
|
||||
SPARE_CONTROL,
|
||||
HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15);
|
||||
HAL_REG_WRITE(soc, reg_addr, reg_val);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* hal_set_ba_aging_timeout_be - Set BA Aging timeout
|
||||
*
|
||||
* @hal_soc: Opaque HAL SOC handle
|
||||
* @ac: Access category
|
||||
* ac: 0 - Background, 1 - Best Effort, 2 - Video, 3 - Voice
|
||||
* @value: Input value to set
|
||||
*/
|
||||
static inline
|
||||
void hal_set_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl,
|
||||
uint8_t ac, uint32_t value)
|
||||
{
|
||||
struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
|
||||
|
||||
switch (ac) {
|
||||
case WME_AC_BE:
|
||||
HAL_REG_WRITE(soc,
|
||||
HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(
|
||||
REO_REG_REG_BASE),
|
||||
value * 1000);
|
||||
break;
|
||||
case WME_AC_BK:
|
||||
HAL_REG_WRITE(soc,
|
||||
HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(
|
||||
REO_REG_REG_BASE),
|
||||
value * 1000);
|
||||
break;
|
||||
case WME_AC_VI:
|
||||
HAL_REG_WRITE(soc,
|
||||
HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(
|
||||
REO_REG_REG_BASE),
|
||||
value * 1000);
|
||||
break;
|
||||
case WME_AC_VO:
|
||||
HAL_REG_WRITE(soc,
|
||||
HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(
|
||||
REO_REG_REG_BASE),
|
||||
value * 1000);
|
||||
break;
|
||||
default:
|
||||
QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
|
||||
"Invalid AC: %d\n", ac);
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* _HAL_BE_GENERIC_API_H_ */
|
||||
|
||||
Reference in New Issue
Block a user