diff --git a/hal/wifi3.0/be/hal_be_api.h b/hal/wifi3.0/be/hal_be_api.h index 0448973e29..861e603f6b 100644 --- a/hal/wifi3.0/be/hal_be_api.h +++ b/hal/wifi3.0/be/hal_be_api.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -23,26 +23,6 @@ #include "hal_hw_headers.h" #include "hal_rx.h" -struct hal_hw_cc_config { - uint32_t lut_base_addr_31_0; - uint32_t cc_global_en:1, - page_4k_align:1, - cookie_offset_msb:5, - cookie_page_msb:5, - lut_base_addr_39_32:8, - wbm2sw6_cc_en:1, - wbm2sw5_cc_en:1, - wbm2sw4_cc_en:1, - wbm2sw3_cc_en:1, - wbm2sw2_cc_en:1, - wbm2sw1_cc_en:1, - wbm2sw0_cc_en:1, - wbm2fw_cc_en:1, - error_path_cookie_conv_en:1, - release_path_cookie_conv_en:1, - reserved:2; -}; - #define HAL_RX_MSDU_EXT_DESC_INFO_GET(msdu_details_ptr) \ ((struct rx_msdu_ext_desc_info *) \ _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ diff --git a/hal/wifi3.0/be/hal_be_generic_api.c b/hal/wifi3.0/be/hal_be_generic_api.c index 6adb40094c..d7ccba5b7b 100644 --- a/hal/wifi3.0/be/hal_be_generic_api.c +++ b/hal/wifi3.0/be/hal_be_generic_api.c @@ -296,155 +296,6 @@ static uint8_t hal_get_wbm_internal_error_generic_be(void *hal_desc) HAL_WBM_INTERNAL_ERROR_LSB; } -/** - * hal_setup_link_idle_list_generic_be - Setup scattered idle list using the - * buffer list provided - * - * @hal_soc: Opaque HAL SOC handle - * @scatter_bufs_base_paddr: Array of physical base addresses - * @scatter_bufs_base_vaddr: Array of virtual base addresses - * @num_scatter_bufs: Number of scatter buffers in the above lists - * @scatter_buf_size: Size of each scatter buffer - * @last_buf_end_offset: Offset to the last entry - * @num_entries: Total entries of all scatter bufs - * - * Return: None - */ -static void -hal_setup_link_idle_list_generic_be(struct hal_soc *soc, - qdf_dma_addr_t scatter_bufs_base_paddr[], - void *scatter_bufs_base_vaddr[], - uint32_t num_scatter_bufs, - uint32_t scatter_buf_size, - uint32_t last_buf_end_offset, - uint32_t num_entries) -{ - int i; - uint32_t *prev_buf_link_ptr = NULL; - uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size; - uint32_t val; - - /* Link the scatter buffers */ - for (i = 0; i < num_scatter_bufs; i++) { - if (i > 0) { - prev_buf_link_ptr[0] = - scatter_bufs_base_paddr[i] & 0xffffffff; - prev_buf_link_ptr[1] = HAL_SM( - HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, - BASE_ADDRESS_39_32, - ((uint64_t)(scatter_bufs_base_paddr[i]) - >> 32)) | HAL_SM( - HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, - ADDRESS_MATCH_TAG, - ADDRESS_MATCH_TAG_VAL); - } - prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] + - scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE); - } - - /* TBD: Register programming partly based on MLD & the rest based on - * inputs from HW team. Not complete yet. - */ - - reg_scatter_buf_size = (scatter_buf_size - - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) / 64; - reg_tot_scatter_buf_size = ((scatter_buf_size - - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs) / 64; - - HAL_REG_WRITE(soc, - HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR( - WBM_REG_REG_BASE), - HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, SCATTER_BUFFER_SIZE, - reg_scatter_buf_size) | - HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, LINK_DESC_IDLE_LIST_MODE, - 0x1)); - - HAL_REG_WRITE(soc, - HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR( - WBM_REG_REG_BASE), - HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE, - SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST, - reg_tot_scatter_buf_size)); - - HAL_REG_WRITE(soc, - HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR( - WBM_REG_REG_BASE), - scatter_bufs_base_paddr[0] & 0xffffffff); - - HAL_REG_WRITE(soc, - HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR( - WBM_REG_REG_BASE), - ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) & - HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK); - - HAL_REG_WRITE(soc, - HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR( - WBM_REG_REG_BASE), - HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, - BASE_ADDRESS_39_32, ((uint64_t)(scatter_bufs_base_paddr[0]) - >> 32)) | - HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, - ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL)); - - /* ADDRESS_MATCH_TAG field in the above register is expected to match - * with the upper bits of link pointer. The above write sets this field - * to zero and we are also setting the upper bits of link pointers to - * zero while setting up the link list of scatter buffers above - */ - - /* Setup head and tail pointers for the idle list */ - HAL_REG_WRITE(soc, - HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR( - WBM_REG_REG_BASE), - scatter_bufs_base_paddr[num_scatter_bufs - 1] & 0xffffffff); - HAL_REG_WRITE(soc, - HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR( - WBM_REG_REG_BASE), - HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, - BUFFER_ADDRESS_39_32, - ((uint64_t)(scatter_bufs_base_paddr[num_scatter_bufs - 1]) - >> 32)) | - HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, - HEAD_POINTER_OFFSET, last_buf_end_offset >> 2)); - - HAL_REG_WRITE(soc, - HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR( - WBM_REG_REG_BASE), - scatter_bufs_base_paddr[0] & 0xffffffff); - - HAL_REG_WRITE(soc, - HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR( - WBM_REG_REG_BASE), - scatter_bufs_base_paddr[0] & 0xffffffff); - HAL_REG_WRITE(soc, - HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR( - WBM_REG_REG_BASE), - HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, - BUFFER_ADDRESS_39_32, - ((uint64_t)(scatter_bufs_base_paddr[0]) >> - 32)) | HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, - TAIL_POINTER_OFFSET, 0)); - - HAL_REG_WRITE(soc, - HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR( - WBM_REG_REG_BASE), - 2 * num_entries); - - /* Set RING_ID_DISABLE */ - val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1); - - /* - * SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence - * check the presence of the bit before toggling it. - */ -#ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK - val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1); -#endif - HAL_REG_WRITE(soc, - HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(WBM_REG_REG_BASE), - val); -} - /** * hal_rx_wbm_err_src_get_be() - Get WBM error source from descriptor * @ring_desc: ring descriptor @@ -757,125 +608,9 @@ static uint8_t hal_rx_reo_buf_type_get_be(hal_ring_desc_t rx_desc) void hal_cookie_conversion_reg_cfg_be(hal_soc_handle_t hal_soc_hdl, struct hal_hw_cc_config *cc_cfg) { - uint32_t reg_addr, reg_val = 0; - struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; + struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; - /* REO CFG */ - reg_addr = HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(REO_REG_REG_BASE); - reg_val = cc_cfg->lut_base_addr_31_0; - HAL_REG_WRITE(soc, reg_addr, reg_val); - - reg_addr = HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(REO_REG_REG_BASE); - reg_val = 0; - reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, - SW_COOKIE_CONVERT_GLOBAL_ENABLE, - cc_cfg->cc_global_en); - reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, - SW_COOKIE_CONVERT_ENABLE, - cc_cfg->cc_global_en); - reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, - PAGE_ALIGNMENT, - cc_cfg->page_4k_align); - reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, - COOKIE_OFFSET_MSB, - cc_cfg->cookie_offset_msb); - reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, - COOKIE_PAGE_MSB, - cc_cfg->cookie_page_msb); - reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, - CMEM_LUT_BASE_ADDR_39_32, - cc_cfg->lut_base_addr_39_32); - HAL_REG_WRITE(soc, reg_addr, reg_val); - - /* WBM CFG */ - reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(WBM_REG_REG_BASE); - reg_val = cc_cfg->lut_base_addr_31_0; - HAL_REG_WRITE(soc, reg_addr, reg_val); - - reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(WBM_REG_REG_BASE); - reg_val = 0; - reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, - PAGE_ALIGNMENT, - cc_cfg->page_4k_align); - reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, - COOKIE_OFFSET_MSB, - cc_cfg->cookie_offset_msb); - reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, - COOKIE_PAGE_MSB, - cc_cfg->cookie_page_msb); - reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, - CMEM_LUT_BASE_ADDR_39_32, - cc_cfg->lut_base_addr_39_32); - HAL_REG_WRITE(soc, reg_addr, reg_val); - - /* - * WCSS_UMAC_WBM_R0_SW_COOKIE_CONVERT_CFG default value is 0x1FE, - */ - reg_addr = HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(WBM_REG_REG_BASE); - reg_val = 0; - reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, - WBM_COOKIE_CONV_GLOBAL_ENABLE, - cc_cfg->cc_global_en); - reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, - WBM2SW6_COOKIE_CONVERSION_EN, - cc_cfg->wbm2sw6_cc_en); - reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, - WBM2SW5_COOKIE_CONVERSION_EN, - cc_cfg->wbm2sw5_cc_en); - reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, - WBM2SW4_COOKIE_CONVERSION_EN, - cc_cfg->wbm2sw4_cc_en); - reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, - WBM2SW3_COOKIE_CONVERSION_EN, - cc_cfg->wbm2sw3_cc_en); - reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, - WBM2SW2_COOKIE_CONVERSION_EN, - cc_cfg->wbm2sw2_cc_en); - reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, - WBM2SW1_COOKIE_CONVERSION_EN, - cc_cfg->wbm2sw1_cc_en); - reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, - WBM2SW0_COOKIE_CONVERSION_EN, - cc_cfg->wbm2sw0_cc_en); - reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, - WBM2FW_COOKIE_CONVERSION_EN, - cc_cfg->wbm2fw_cc_en); - HAL_REG_WRITE(soc, reg_addr, reg_val); - -#ifdef HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK - reg_addr = HWIO_WBM_R0_WBM_CFG_2_ADDR(WBM_REG_REG_BASE); - reg_val = 0; - reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, - COOKIE_DEBUG_SEL, - cc_cfg->cc_global_en); - - reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, - COOKIE_CONV_INDICATION_EN, - cc_cfg->cc_global_en); - - reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, - ERROR_PATH_COOKIE_CONV_EN, - cc_cfg->error_path_cookie_conv_en); - - reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, - RELEASE_PATH_COOKIE_CONV_EN, - cc_cfg->release_path_cookie_conv_en); - - HAL_REG_WRITE(soc, reg_addr, reg_val); -#endif -#ifdef DP_HW_COOKIE_CONVERT_EXCEPTION - /* - * To enable indication for HW cookie conversion done or not for - * WBM, WCSS_UMAC_WBM_R0_MISC_CONTROL spare_control field 15th - * bit spare_control[15] should be set. - */ - reg_addr = HWIO_WBM_R0_MISC_CONTROL_ADDR(WBM_REG_REG_BASE); - reg_val = HAL_REG_READ(soc, reg_addr); - reg_val |= HAL_SM(HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL, - SPARE_CONTROL, - HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15); - HAL_REG_WRITE(soc, reg_addr, reg_val); -#endif + hal_soc->ops->hal_cookie_conversion_reg_cfg_be(hal_soc_hdl, cc_cfg); } qdf_export_symbol(hal_cookie_conversion_reg_cfg_be); @@ -1053,14 +788,9 @@ void hal_hw_txrx_default_ops_attach_be(struct hal_soc *hal_soc) hal_soc->ops->hal_get_rx_max_ba_window = hal_get_rx_max_ba_window_be; hal_soc->ops->hal_set_link_desc_addr = hal_set_link_desc_addr_be; hal_soc->ops->hal_tx_init_data_ring = hal_tx_init_data_ring_be; - hal_soc->ops->hal_get_ba_aging_timeout = hal_get_ba_aging_timeout_be; - hal_soc->ops->hal_set_ba_aging_timeout = hal_set_ba_aging_timeout_be; hal_soc->ops->hal_get_reo_reg_base_offset = hal_get_reo_reg_base_offset_be; - hal_soc->ops->hal_setup_link_idle_list = - hal_setup_link_idle_list_generic_be; hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_be; - hal_soc->ops->hal_rx_reo_buf_paddr_get = hal_rx_reo_buf_paddr_get_be; hal_soc->ops->hal_rx_msdu_link_desc_set = hal_rx_msdu_link_desc_set_be; hal_soc->ops->hal_rx_buf_cookie_rbm_get = hal_rx_buf_cookie_rbm_get_be; diff --git a/hal/wifi3.0/be/hal_be_generic_api.h b/hal/wifi3.0/be/hal_be_generic_api.h index 75f3468bc7..7bee6fd845 100644 --- a/hal/wifi3.0/be/hal_be_generic_api.h +++ b/hal/wifi3.0/be/hal_be_generic_api.h @@ -2737,4 +2737,456 @@ static void hal_reo_shared_qaddr_detach_be(hal_soc_handle_t hal_soc_hdl) hal->reo_qref.non_mlo_reo_qref_table_paddr, 0); } #endif + +/** + * hal_tx_vdev_mismatch_routing_set - set vdev mismatch exception routing + * @hal_soc: HAL SoC context + * @config: HAL_TX_VDEV_MISMATCH_TQM_NOTIFY - route via TQM + * HAL_TX_VDEV_MISMATCH_FW_NOTIFY - route via FW + * + * Return: void + */ +#ifdef HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK +static inline void +hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl, + enum hal_tx_vdev_mismatch_notify + config) +{ + struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; + uint32_t reg_addr, reg_val = 0; + uint32_t val = 0; + + reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE); + + val = HAL_REG_READ(hal_soc, reg_addr); + + /* reset the corresponding bits in register */ + val &= (~(HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK)); + + /* set config value */ + reg_val = val | (config << + HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_SHFT); + + HAL_REG_WRITE(hal_soc, reg_addr, reg_val); +} +#else +static inline void +hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl, + enum hal_tx_vdev_mismatch_notify + config) +{ +} +#endif + +/** + * hal_tx_mcast_mlo_reinject_routing_set - set MLO multicast reinject routing + * @hal_soc: HAL SoC context + * @config: HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY - route via FW + * HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY - route via TQM + * + * Return: void + */ +#if defined(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK) && \ + defined(WLAN_MCAST_MLO) +static inline void +hal_tx_mcast_mlo_reinject_routing_set_generic_be( + hal_soc_handle_t hal_soc_hdl, + enum hal_tx_mcast_mlo_reinject_notify config) +{ + struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; + uint32_t reg_addr, reg_val = 0; + uint32_t val = 0; + + reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE); + val = HAL_REG_READ(hal_soc, reg_addr); + + /* reset the corresponding bits in register */ + val &= (~(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK)); + + /* set config value */ + reg_val = val | (config << HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_SHFT); + + HAL_REG_WRITE(hal_soc, reg_addr, reg_val); +} +#else +static inline void +hal_tx_mcast_mlo_reinject_routing_set_generic_be( + hal_soc_handle_t hal_soc_hdl, + enum hal_tx_mcast_mlo_reinject_notify config) +{ +} +#endif + +/** + * hal_get_ba_aging_timeout_be - Get BA Aging timeout + * + * @hal_soc: Opaque HAL SOC handle + * @ac: Access category + * @value: window size to get + */ + +static inline +void hal_get_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl, + uint8_t ac, uint32_t *value) +{ + struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; + + switch (ac) { + case WME_AC_BE: + *value = HAL_REG_READ(soc, + HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( + REO_REG_REG_BASE)) / 1000; + break; + case WME_AC_BK: + *value = HAL_REG_READ(soc, + HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( + REO_REG_REG_BASE)) / 1000; + break; + case WME_AC_VI: + *value = HAL_REG_READ(soc, + HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( + REO_REG_REG_BASE)) / 1000; + break; + case WME_AC_VO: + *value = HAL_REG_READ(soc, + HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( + REO_REG_REG_BASE)) / 1000; + break; + default: + QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, + "Invalid AC: %d\n", ac); + } +} + +/** + * hal_setup_link_idle_list_generic_be - Setup scattered idle list using the + * buffer list provided + * + * @hal_soc: Opaque HAL SOC handle + * @scatter_bufs_base_paddr: Array of physical base addresses + * @scatter_bufs_base_vaddr: Array of virtual base addresses + * @num_scatter_bufs: Number of scatter buffers in the above lists + * @scatter_buf_size: Size of each scatter buffer + * @last_buf_end_offset: Offset to the last entry + * @num_entries: Total entries of all scatter bufs + * + * Return: None + */ +static inline void +hal_setup_link_idle_list_generic_be(struct hal_soc *soc, + qdf_dma_addr_t scatter_bufs_base_paddr[], + void *scatter_bufs_base_vaddr[], + uint32_t num_scatter_bufs, + uint32_t scatter_buf_size, + uint32_t last_buf_end_offset, + uint32_t num_entries) +{ + int i; + uint32_t *prev_buf_link_ptr = NULL; + uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size; + uint32_t val; + + /* Link the scatter buffers */ + for (i = 0; i < num_scatter_bufs; i++) { + if (i > 0) { + prev_buf_link_ptr[0] = + scatter_bufs_base_paddr[i] & 0xffffffff; + prev_buf_link_ptr[1] = HAL_SM( + HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, + BASE_ADDRESS_39_32, + ((uint64_t)(scatter_bufs_base_paddr[i]) + >> 32)) | HAL_SM( + HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, + ADDRESS_MATCH_TAG, + ADDRESS_MATCH_TAG_VAL); + } + prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] + + scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE); + } + + /* TBD: Register programming partly based on MLD & the rest based on + * inputs from HW team. Not complete yet. + */ + + reg_scatter_buf_size = (scatter_buf_size - + WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) / 64; + reg_tot_scatter_buf_size = ((scatter_buf_size - + WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs) / 64; + + HAL_REG_WRITE(soc, + HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR( + WBM_REG_REG_BASE), + HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, SCATTER_BUFFER_SIZE, + reg_scatter_buf_size) | + HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, LINK_DESC_IDLE_LIST_MODE, + 0x1)); + + HAL_REG_WRITE(soc, + HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR( + WBM_REG_REG_BASE), + HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE, + SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST, + reg_tot_scatter_buf_size)); + + HAL_REG_WRITE(soc, + HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR( + WBM_REG_REG_BASE), + scatter_bufs_base_paddr[0] & 0xffffffff); + + HAL_REG_WRITE(soc, + HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR( + WBM_REG_REG_BASE), + ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) & + HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK); + + HAL_REG_WRITE(soc, + HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR( + WBM_REG_REG_BASE), + HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, + BASE_ADDRESS_39_32, ((uint64_t)(scatter_bufs_base_paddr[0]) + >> 32)) | + HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, + ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL)); + + /* ADDRESS_MATCH_TAG field in the above register is expected to match + * with the upper bits of link pointer. The above write sets this field + * to zero and we are also setting the upper bits of link pointers to + * zero while setting up the link list of scatter buffers above + */ + + /* Setup head and tail pointers for the idle list */ + HAL_REG_WRITE(soc, + HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR( + WBM_REG_REG_BASE), + scatter_bufs_base_paddr[num_scatter_bufs - 1] & 0xffffffff); + HAL_REG_WRITE(soc, + HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR( + WBM_REG_REG_BASE), + HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, + BUFFER_ADDRESS_39_32, + ((uint64_t)(scatter_bufs_base_paddr[num_scatter_bufs - 1]) + >> 32)) | + HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, + HEAD_POINTER_OFFSET, last_buf_end_offset >> 2)); + + HAL_REG_WRITE(soc, + HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR( + WBM_REG_REG_BASE), + scatter_bufs_base_paddr[0] & 0xffffffff); + + HAL_REG_WRITE(soc, + HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR( + WBM_REG_REG_BASE), + scatter_bufs_base_paddr[0] & 0xffffffff); + HAL_REG_WRITE(soc, + HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR( + WBM_REG_REG_BASE), + HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, + BUFFER_ADDRESS_39_32, + ((uint64_t)(scatter_bufs_base_paddr[0]) >> + 32)) | HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, + TAIL_POINTER_OFFSET, 0)); + + HAL_REG_WRITE(soc, + HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR( + WBM_REG_REG_BASE), + 2 * num_entries); + + /* Set RING_ID_DISABLE */ + val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1); + + /* + * SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence + * check the presence of the bit before toggling it. + */ +#ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK + val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1); +#endif + HAL_REG_WRITE(soc, + HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(WBM_REG_REG_BASE), + val); +} + +#ifdef DP_HW_COOKIE_CONVERT_EXCEPTION +#define HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15 0x8000 +#endif + +/** + * hal_cookie_conversion_reg_cfg_generic_be() - set cookie conversion relevant register + * for REO/WBM + * @soc: HAL soc handle + * @cc_cfg: structure pointer for HW cookie conversion configuration + * + * Return: None + */ +static inline +void hal_cookie_conversion_reg_cfg_generic_be(hal_soc_handle_t hal_soc_hdl, + struct hal_hw_cc_config *cc_cfg) +{ + uint32_t reg_addr, reg_val = 0; + struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; + + /* REO CFG */ + reg_addr = HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(REO_REG_REG_BASE); + reg_val = cc_cfg->lut_base_addr_31_0; + HAL_REG_WRITE(soc, reg_addr, reg_val); + + reg_addr = HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(REO_REG_REG_BASE); + reg_val = 0; + reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, + SW_COOKIE_CONVERT_GLOBAL_ENABLE, + cc_cfg->cc_global_en); + reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, + SW_COOKIE_CONVERT_ENABLE, + cc_cfg->cc_global_en); + reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, + PAGE_ALIGNMENT, + cc_cfg->page_4k_align); + reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, + COOKIE_OFFSET_MSB, + cc_cfg->cookie_offset_msb); + reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, + COOKIE_PAGE_MSB, + cc_cfg->cookie_page_msb); + reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, + CMEM_LUT_BASE_ADDR_39_32, + cc_cfg->lut_base_addr_39_32); + HAL_REG_WRITE(soc, reg_addr, reg_val); + + /* WBM CFG */ + reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(WBM_REG_REG_BASE); + reg_val = cc_cfg->lut_base_addr_31_0; + HAL_REG_WRITE(soc, reg_addr, reg_val); + + reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(WBM_REG_REG_BASE); + reg_val = 0; + reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, + PAGE_ALIGNMENT, + cc_cfg->page_4k_align); + reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, + COOKIE_OFFSET_MSB, + cc_cfg->cookie_offset_msb); + reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, + COOKIE_PAGE_MSB, + cc_cfg->cookie_page_msb); + reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, + CMEM_LUT_BASE_ADDR_39_32, + cc_cfg->lut_base_addr_39_32); + HAL_REG_WRITE(soc, reg_addr, reg_val); + + /* + * WCSS_UMAC_WBM_R0_SW_COOKIE_CONVERT_CFG default value is 0x1FE, + */ + reg_addr = HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(WBM_REG_REG_BASE); + reg_val = 0; + reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, + WBM_COOKIE_CONV_GLOBAL_ENABLE, + cc_cfg->cc_global_en); + reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, + WBM2SW6_COOKIE_CONVERSION_EN, + cc_cfg->wbm2sw6_cc_en); + reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, + WBM2SW5_COOKIE_CONVERSION_EN, + cc_cfg->wbm2sw5_cc_en); + reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, + WBM2SW4_COOKIE_CONVERSION_EN, + cc_cfg->wbm2sw4_cc_en); + reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, + WBM2SW3_COOKIE_CONVERSION_EN, + cc_cfg->wbm2sw3_cc_en); + reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, + WBM2SW2_COOKIE_CONVERSION_EN, + cc_cfg->wbm2sw2_cc_en); + reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, + WBM2SW1_COOKIE_CONVERSION_EN, + cc_cfg->wbm2sw1_cc_en); + reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, + WBM2SW0_COOKIE_CONVERSION_EN, + cc_cfg->wbm2sw0_cc_en); + reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, + WBM2FW_COOKIE_CONVERSION_EN, + cc_cfg->wbm2fw_cc_en); + HAL_REG_WRITE(soc, reg_addr, reg_val); + +#ifdef HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK + reg_addr = HWIO_WBM_R0_WBM_CFG_2_ADDR(WBM_REG_REG_BASE); + reg_val = 0; + reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, + COOKIE_DEBUG_SEL, + cc_cfg->cc_global_en); + + reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, + COOKIE_CONV_INDICATION_EN, + cc_cfg->cc_global_en); + + reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, + ERROR_PATH_COOKIE_CONV_EN, + cc_cfg->error_path_cookie_conv_en); + + reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, + RELEASE_PATH_COOKIE_CONV_EN, + cc_cfg->release_path_cookie_conv_en); + + HAL_REG_WRITE(soc, reg_addr, reg_val); +#endif +#ifdef DP_HW_COOKIE_CONVERT_EXCEPTION + /* + * To enable indication for HW cookie conversion done or not for + * WBM, WCSS_UMAC_WBM_R0_MISC_CONTROL spare_control field 15th + * bit spare_control[15] should be set. + */ + reg_addr = HWIO_WBM_R0_MISC_CONTROL_ADDR(WBM_REG_REG_BASE); + reg_val = HAL_REG_READ(soc, reg_addr); + reg_val |= HAL_SM(HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL, + SPARE_CONTROL, + HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15); + HAL_REG_WRITE(soc, reg_addr, reg_val); +#endif +} + +/** + * hal_set_ba_aging_timeout_be - Set BA Aging timeout + * + * @hal_soc: Opaque HAL SOC handle + * @ac: Access category + * ac: 0 - Background, 1 - Best Effort, 2 - Video, 3 - Voice + * @value: Input value to set + */ +static inline +void hal_set_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl, + uint8_t ac, uint32_t value) +{ + struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; + + switch (ac) { + case WME_AC_BE: + HAL_REG_WRITE(soc, + HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( + REO_REG_REG_BASE), + value * 1000); + break; + case WME_AC_BK: + HAL_REG_WRITE(soc, + HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( + REO_REG_REG_BASE), + value * 1000); + break; + case WME_AC_VI: + HAL_REG_WRITE(soc, + HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( + REO_REG_REG_BASE), + value * 1000); + break; + case WME_AC_VO: + HAL_REG_WRITE(soc, + HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( + REO_REG_REG_BASE), + value * 1000); + break; + default: + QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, + "Invalid AC: %d\n", ac); + } +} + #endif /* _HAL_BE_GENERIC_API_H_ */ diff --git a/hal/wifi3.0/be/hal_be_reo.c b/hal/wifi3.0/be/hal_be_reo.c index 440f6205ac..4eb91f14ea 100644 --- a/hal/wifi3.0/be/hal_be_reo.c +++ b/hal/wifi3.0/be/hal_be_reo.c @@ -199,91 +199,6 @@ void hal_reo_qdesc_setup_be(hal_soc_handle_t hal_soc_hdl, int tid, qdf_export_symbol(hal_reo_qdesc_setup_be); -/** - * hal_get_ba_aging_timeout_be - Get BA Aging timeout - * - * @hal_soc: Opaque HAL SOC handle - * @ac: Access category - * @value: window size to get - */ -void hal_get_ba_aging_timeout_be(hal_soc_handle_t hal_soc_hdl, uint8_t ac, - uint32_t *value) -{ - struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; - - switch (ac) { - case WME_AC_BE: - *value = HAL_REG_READ(soc, - HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( - REO_REG_REG_BASE)) / 1000; - break; - case WME_AC_BK: - *value = HAL_REG_READ(soc, - HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( - REO_REG_REG_BASE)) / 1000; - break; - case WME_AC_VI: - *value = HAL_REG_READ(soc, - HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( - REO_REG_REG_BASE)) / 1000; - break; - case WME_AC_VO: - *value = HAL_REG_READ(soc, - HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( - REO_REG_REG_BASE)) / 1000; - break; - default: - QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, - "Invalid AC: %d\n", ac); - } -} -qdf_export_symbol(hal_get_ba_aging_timeout_be); - -/** - * hal_set_ba_aging_timeout_be - Set BA Aging timeout - * - * @hal_soc: Opaque HAL SOC handle - * @ac: Access category - * ac: 0 - Background, 1 - Best Effort, 2 - Video, 3 - Voice - * @value: Input value to set - */ -void hal_set_ba_aging_timeout_be(hal_soc_handle_t hal_soc_hdl, uint8_t ac, - uint32_t value) -{ - struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; - - switch (ac) { - case WME_AC_BE: - HAL_REG_WRITE(soc, - HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( - REO_REG_REG_BASE), - value * 1000); - break; - case WME_AC_BK: - HAL_REG_WRITE(soc, - HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( - REO_REG_REG_BASE), - value * 1000); - break; - case WME_AC_VI: - HAL_REG_WRITE(soc, - HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( - REO_REG_REG_BASE), - value * 1000); - break; - case WME_AC_VO: - HAL_REG_WRITE(soc, - HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( - REO_REG_REG_BASE), - value * 1000); - break; - default: - QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, - "Invalid AC: %d\n", ac); - } -} -qdf_export_symbol(hal_set_ba_aging_timeout_be); - static void hal_reo_cmd_set_descr_addr_be(uint32_t *reo_desc, enum hal_reo_cmd_type type, diff --git a/hal/wifi3.0/be/hal_be_reo.h b/hal/wifi3.0/be/hal_be_reo.h index e1252451cb..93cbca56d0 100644 --- a/hal/wifi3.0/be/hal_be_reo.h +++ b/hal/wifi3.0/be/hal_be_reo.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2017-2019, 2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -44,10 +44,6 @@ static inline void hal_update_stats_counter_index(uint32_t *reo_queue_desc, #endif /* Proto-types */ -void hal_get_ba_aging_timeout_be(hal_soc_handle_t hal_soc_hdl, uint8_t ac, - uint32_t *value); -void hal_set_ba_aging_timeout_be(hal_soc_handle_t hal_soc_hdl, uint8_t ac, - uint32_t value); uint32_t hal_get_reo_reg_base_offset_be(void); int hal_reo_send_cmd_be(hal_soc_handle_t hal_soc_hdl, diff --git a/hal/wifi3.0/be/hal_be_tx.h b/hal/wifi3.0/be/hal_be_tx.h index e03707c34e..92a9cb0614 100644 --- a/hal/wifi3.0/be/hal_be_tx.h +++ b/hal/wifi3.0/be/hal_be_tx.h @@ -60,16 +60,6 @@ enum hal_tx_mcast_ctrl { HAL_TX_MCAST_CTRL_NO_SPECIAL, }; -/** - * enum hal_tx_vdev_mismatch_notify - * @HAL_TX_VDEV_MISMATCH_TQM_NOTIFY: vdev mismatch exception routed to TQM - * @HAL_TX_VDEV_MISMATCH_FW_NOTIFY: vdev mismatch exception routed to FW - */ -enum hal_tx_vdev_mismatch_notify { - HAL_TX_VDEV_MISMATCH_TQM_NOTIFY = 0, - HAL_TX_VDEV_MISMATCH_FW_NOTIFY, -}; - /* enum hal_tx_notify_frame_type - TX notify frame type * @NO_TX_NOTIFY: Not a notify frame * @TX_HARD_NOTIFY: Hard notify TX frame @@ -83,16 +73,6 @@ enum hal_tx_notify_frame_type { TX_SEMI_HARD_NOTIFY_E = 3 }; -/** - * enum hal_tx_mcast_mlo_reinject_notify - * @HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY: MLO Mcast reinject routed to FW - * @HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY: MLO Mcast reinject routed to TQM - */ -enum hal_tx_mcast_mlo_reinject_notify { - HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY = 0, - HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY, -}; - /*--------------------------------------------------------------------------- * Structures * --------------------------------------------------------------------------- @@ -748,36 +728,10 @@ hal_tx_config_rbm_mapping_be(hal_soc_handle_t hal_soc_hdl, hal_ring_handle_t hal_ring_hdl, uint8_t rbm_id) { - struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; - uint32_t reg_addr = 0; - uint32_t reg_val = 0; - uint32_t val = 0; - uint8_t ring_num; - enum hal_ring_type ring_type; - ring_type = srng->ring_type; - ring_num = hal_soc->hw_srng_table[ring_type].start_ring_id; - ring_num = srng->ring_id - ring_num; - - reg_addr = HWIO_TCL_R0_RBM_MAPPING0_ADDR(MAC_TCL_REG_REG_BASE); - - if (ring_type == PPE2TCL) - ring_num = ring_num + RBM_PPE2TCL_OFFSET; - else if (ring_type == TCL_CMD_CREDIT) - ring_num = ring_num + RBM_TCL_CMD_CREDIT_OFFSET; - - /* get current value stored in register address */ - val = HAL_REG_READ(hal_soc, reg_addr); - - /* mask out other stored value */ - val &= (~(RBM_MAPPING_BMSK << (RBM_MAPPING_SHFT * ring_num))); - - reg_val = val | ((RBM_MAPPING_BMSK & rbm_id) << - (RBM_MAPPING_SHFT * ring_num)); - - /* write rbm mapped value to register address */ - HAL_REG_WRITE(hal_soc, reg_addr, reg_val); + hal_soc->ops->hal_tx_config_rbm_mapping_be(hal_soc_hdl, hal_ring_hdl, + rbm_id); } #else static inline void @@ -928,21 +882,8 @@ hal_tx_vdev_mismatch_routing_set(hal_soc_handle_t hal_soc_hdl, enum hal_tx_vdev_mismatch_notify config) { struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; - uint32_t reg_addr, reg_val = 0; - uint32_t val = 0; - reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE); - - val = HAL_REG_READ(hal_soc, reg_addr); - - /* reset the corresponding bits in register */ - val &= (~(HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK)); - - /* set config value */ - reg_val = val | (config << - HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_SHFT); - - HAL_REG_WRITE(hal_soc, reg_addr, reg_val); + hal_soc->ops->hal_tx_vdev_mismatch_routing_set(hal_soc_hdl, config); } #else static inline void @@ -968,19 +909,8 @@ hal_tx_mcast_mlo_reinject_routing_set( enum hal_tx_mcast_mlo_reinject_notify config) { struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; - uint32_t reg_addr, reg_val = 0; - uint32_t val = 0; - - reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE); - val = HAL_REG_READ(hal_soc, reg_addr); - - /* reset the corresponding bits in register */ - val &= (~(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK)); - - /* set config value */ - reg_val = val | (config << HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_SHFT); - - HAL_REG_WRITE(hal_soc, reg_addr, reg_val); + hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set(hal_soc_hdl, + config); } #else static inline void diff --git a/hal/wifi3.0/hal_internal.h b/hal/wifi3.0/hal_internal.h index 8d53b499f3..b0d21a2cdf 100644 --- a/hal/wifi3.0/hal_internal.h +++ b/hal/wifi3.0/hal_internal.h @@ -97,6 +97,26 @@ extern bool is_hal_verbose_debug_enabled; */ #define HAL_GET_NUM_DWORDS(num) ((num) >> 2) +struct hal_hw_cc_config { + uint32_t lut_base_addr_31_0; + uint32_t cc_global_en:1, + page_4k_align:1, + cookie_offset_msb:5, + cookie_page_msb:5, + lut_base_addr_39_32:8, + wbm2sw6_cc_en:1, + wbm2sw5_cc_en:1, + wbm2sw4_cc_en:1, + wbm2sw3_cc_en:1, + wbm2sw2_cc_en:1, + wbm2sw1_cc_en:1, + wbm2sw0_cc_en:1, + wbm2fw_cc_en:1, + error_path_cookie_conv_en:1, + release_path_cookie_conv_en:1, + reserved:2; +}; + /* * dp_hal_soc - opaque handle for DP HAL soc */ @@ -765,6 +785,26 @@ enum hal_reo_cmd_type { CMD_UPDATE_RX_REO_QUEUE = 5 }; +/** + * enum hal_tx_mcast_mlo_reinject_notify + * @HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY: MLO Mcast reinject routed to FW + * @HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY: MLO Mcast reinject routed to TQM + */ +enum hal_tx_mcast_mlo_reinject_notify { + HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY = 0, + HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY, +}; + +/** + * enum hal_tx_vdev_mismatch_notify + * @HAL_TX_VDEV_MISMATCH_TQM_NOTIFY: vdev mismatch exception routed to TQM + * @HAL_TX_VDEV_MISMATCH_FW_NOTIFY: vdev mismatch exception routed to FW + */ +enum hal_tx_vdev_mismatch_notify { + HAL_TX_VDEV_MISMATCH_TQM_NOTIFY = 0, + HAL_TX_VDEV_MISMATCH_FW_NOTIFY, +}; + struct hal_rx_pkt_capture_flags { uint8_t encrypt_type; uint8_t fragment_flag; @@ -843,6 +883,9 @@ struct hal_hw_txrx_ops { void (*hal_tx_dump_ppe_vp_entry)(hal_soc_handle_t hal_soc_hdl); void (*hal_tx_enable_pri2tid_map)(hal_soc_handle_t hal_soc_hdl, bool value, uint8_t ppe_vp_idx); + void (*hal_tx_config_rbm_mapping_be)(hal_soc_handle_t hal_soc_hdl, + hal_ring_handle_t hal_ring_hdl, + uint8_t rbm_id); /* rx */ uint32_t (*hal_rx_msdu_start_nss_get)(uint8_t *); @@ -1121,6 +1164,14 @@ struct hal_hw_txrx_ops { #endif void (*hal_reo_shared_qaddr_cache_clear)(hal_soc_handle_t hal_soc_hdl); uint32_t (*hal_rx_tlv_l3_type_get)(uint8_t *buf); + void (*hal_tx_vdev_mismatch_routing_set)(hal_soc_handle_t hal_soc_hdl, + enum hal_tx_vdev_mismatch_notify config); + void (*hal_tx_mcast_mlo_reinject_routing_set)( + hal_soc_handle_t hal_soc_hdl, + enum hal_tx_mcast_mlo_reinject_notify config); + void (*hal_cookie_conversion_reg_cfg_be)(hal_soc_handle_t hal_soc_hdl, + struct hal_hw_cc_config + *cc_cfg); }; /** diff --git a/hal/wifi3.0/kiwi/hal_kiwi.c b/hal/wifi3.0/kiwi/hal_kiwi.c index 5ca4703727..4447e845c8 100644 --- a/hal/wifi3.0/kiwi/hal_kiwi.c +++ b/hal/wifi3.0/kiwi/hal_kiwi.c @@ -1841,6 +1841,8 @@ static void hal_hw_txrx_ops_attach_kiwi(struct hal_soc *hal_soc) hal_tx_comp_get_status_generic_be; hal_soc->ops->hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_kiwi; + hal_soc->ops->hal_tx_config_rbm_mapping_be = + hal_tx_config_rbm_mapping_be_kiwi; /* rx */ hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be; @@ -2059,6 +2061,18 @@ static void hal_hw_txrx_ops_attach_kiwi(struct hal_soc *hal_soc) hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; hal_soc->ops->hal_rx_tlv_l3_type_get = hal_rx_tlv_l3_type_get_be; + hal_soc->ops->hal_tx_vdev_mismatch_routing_set = + hal_tx_vdev_mismatch_routing_set_generic_be; + hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set = + hal_tx_mcast_mlo_reinject_routing_set_generic_be; + hal_soc->ops->hal_get_ba_aging_timeout = + hal_get_ba_aging_timeout_be_generic; + hal_soc->ops->hal_setup_link_idle_list = + hal_setup_link_idle_list_generic_be; + hal_soc->ops->hal_cookie_conversion_reg_cfg_be = + hal_cookie_conversion_reg_cfg_generic_be; + hal_soc->ops->hal_set_ba_aging_timeout = + hal_set_ba_aging_timeout_be_generic; }; struct hal_hw_srng_config hw_srng_table_kiwi[] = { diff --git a/hal/wifi3.0/kiwi/hal_kiwi_tx.h b/hal/wifi3.0/kiwi/hal_kiwi_tx.h index bc993250f1..a5e8fe74b3 100644 --- a/hal/wifi3.0/kiwi/hal_kiwi_tx.h +++ b/hal/wifi3.0/kiwi/hal_kiwi_tx.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2021 The Linux Foundation. All rights reserved. - * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -145,3 +145,66 @@ hal_tx_init_cmd_credit_ring_kiwi(hal_soc_handle_t hal_soc_hdl, hal_ring_handle_t hal_ring_hdl) { } + +#ifdef DP_TX_IMPLICIT_RBM_MAPPING + +#define RBM_MAPPING_BMSK HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK +#define RBM_MAPPING_SHFT HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT + +#define RBM_PPE2TCL_OFFSET \ + (HWIO_TCL_R0_RBM_MAPPING0_PPE2TCL1_RING_SHFT >> 2) +#define RBM_TCL_CMD_CREDIT_OFFSET \ + (HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT >> 2) + +/** + * hal_tx_config_rbm_mapping_be() - Update return buffer manager ring id + * @hal_soc: HAL SoC context + * @hal_ring_hdl: Source ring pointer + * @rbm_id: return buffer manager ring id + * + * Return: void + */ +static inline void +hal_tx_config_rbm_mapping_be_kiwi(hal_soc_handle_t hal_soc_hdl, + hal_ring_handle_t hal_ring_hdl, + uint8_t rbm_id) +{ + struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; + struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; + uint32_t reg_addr = 0; + uint32_t reg_val = 0; + uint32_t val = 0; + uint8_t ring_num; + enum hal_ring_type ring_type; + + ring_type = srng->ring_type; + ring_num = hal_soc->hw_srng_table[ring_type].start_ring_id; + ring_num = srng->ring_id - ring_num; + + reg_addr = HWIO_TCL_R0_RBM_MAPPING0_ADDR(MAC_TCL_REG_REG_BASE); + + if (ring_type == PPE2TCL) + ring_num = ring_num + RBM_PPE2TCL_OFFSET; + else if (ring_type == TCL_CMD_CREDIT) + ring_num = ring_num + RBM_TCL_CMD_CREDIT_OFFSET; + + /* get current value stored in register address */ + val = HAL_REG_READ(hal_soc, reg_addr); + + /* mask out other stored value */ + val &= (~(RBM_MAPPING_BMSK << (RBM_MAPPING_SHFT * ring_num))); + + reg_val = val | ((RBM_MAPPING_BMSK & rbm_id) << + (RBM_MAPPING_SHFT * ring_num)); + + /* write rbm mapped value to register address */ + HAL_REG_WRITE(hal_soc, reg_addr, reg_val); +} +#else +static inline void +hal_tx_config_rbm_mapping_be_kiwi(hal_soc_handle_t hal_soc_hdl, + hal_ring_handle_t hal_ring_hdl, + uint8_t rbm_id) +{ +} +#endif diff --git a/hal/wifi3.0/qca5332/hal_5332.c b/hal/wifi3.0/qca5332/hal_5332.c index 5ad61e5052..87bbc00ae9 100644 --- a/hal/wifi3.0/qca5332/hal_5332.c +++ b/hal/wifi3.0/qca5332/hal_5332.c @@ -106,7 +106,7 @@ #endif #define CE_WINDOW_ADDRESS_5332 \ - ((CE_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) + ((CE_CFG_WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) #define UMAC_WINDOW_ADDRESS_5332 \ ((UMAC_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) @@ -1215,7 +1215,7 @@ static inline qdf_iomem_t hal_get_window_address_5332(struct hal_soc *hal_soc, * If offset lies within CE register range, use 2nd window to write * into CE region. */ - } else if ((offset ^ CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) { + } else if ((offset ^ CE_CFG_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) { new_offset = (hal_soc->dev_base_addr + (2 * WINDOW_START) + (offset & WINDOW_RANGE_MASK)); } else { @@ -1466,28 +1466,6 @@ static inline void hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs *pkt_tlvs, } #endif -/* - * hal_tx_dump_ppe_vp_entry_5332() - * @hal_soc_hdl: HAL SoC handle - * - * Return: void - */ -static inline -void hal_tx_dump_ppe_vp_entry_5332(hal_soc_handle_t hal_soc_hdl) -{ - struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; - uint32_t reg_addr, reg_val = 0, i; - - for (i = 0; i < HAL_PPE_VP_ENTRIES_MAX; i++) { - reg_addr = - HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR( - MAC_TCL_REG_REG_BASE, - i); - reg_val = HAL_REG_READ(soc, reg_addr); - hal_verbose_debug("%d: 0x%x\n", i, reg_val); - } -} - /** * hal_rx_dump_pkt_tlvs_5332(): API to print RX Pkt TLVS qca5332 * @hal_soc_hdl: hal_soc handle @@ -1689,19 +1667,6 @@ static uint32_t hal_qca5332_get_reo_qdesc_size(uint32_t ba_window_size, int tid) (10 * sizeof(struct rx_reo_queue_ext)) + sizeof(struct rx_reo_queue_1k); } - -/* - * hal_tx_dump_ppe_vp_entry_5332() - * @hal_soc_hdl: HAL SoC handle - * - * Return: Number of PPE VP entries - */ -static -uint32_t hal_tx_get_num_ppe_vp_tbl_entries_5332(hal_soc_handle_t hal_soc_hdl) -{ - return HAL_PPE_VP_ENTRIES_MAX; -} - /** * hal_rx_tlv_msdu_done_copy_get_5332() - Get msdu done copy bit from rx_tlv * @@ -1728,20 +1693,15 @@ static void hal_hw_txrx_ops_attach_qca5332(struct hal_soc *hal_soc) hal_tx_comp_get_status_generic_be; hal_soc->ops->hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_5332; - hal_soc->ops->hal_tx_set_ppe_cmn_cfg = - hal_tx_set_ppe_cmn_config_5332; - hal_soc->ops->hal_tx_set_ppe_vp_entry = - hal_tx_set_ppe_vp_entry_5332; - hal_soc->ops->hal_tx_set_ppe_pri2tid = - hal_tx_set_ppe_pri2tid_map_5332; - hal_soc->ops->hal_tx_update_ppe_pri2tid = - hal_tx_update_ppe_pri2tid_5332; - hal_soc->ops->hal_tx_dump_ppe_vp_entry = - hal_tx_dump_ppe_vp_entry_5332; - hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries = - hal_tx_get_num_ppe_vp_tbl_entries_5332; - hal_soc->ops->hal_tx_enable_pri2tid_map = - hal_tx_enable_pri2tid_map_5332; + hal_soc->ops->hal_tx_set_ppe_cmn_cfg = NULL; + hal_soc->ops->hal_tx_set_ppe_vp_entry = NULL; + hal_soc->ops->hal_tx_set_ppe_pri2tid = NULL; + hal_soc->ops->hal_tx_update_ppe_pri2tid = NULL; + hal_soc->ops->hal_tx_dump_ppe_vp_entry = NULL; + hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries = NULL; + hal_soc->ops->hal_tx_enable_pri2tid_map = NULL; + hal_soc->ops->hal_tx_config_rbm_mapping_be = + hal_tx_config_rbm_mapping_be_5332; /* rx */ hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be; @@ -1953,6 +1913,18 @@ static void hal_hw_txrx_ops_attach_qca5332(struct hal_soc *hal_soc) hal_txmon_status_free_buffer_generic_be; #endif /* QCA_MONITOR_2_0_SUPPORT */ hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; + hal_soc->ops->hal_tx_vdev_mismatch_routing_set = + hal_tx_vdev_mismatch_routing_set_generic_be; + hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set = + hal_tx_mcast_mlo_reinject_routing_set_generic_be; + hal_soc->ops->hal_get_ba_aging_timeout = + hal_get_ba_aging_timeout_be_generic; + hal_soc->ops->hal_setup_link_idle_list = + hal_setup_link_idle_list_generic_be; + hal_soc->ops->hal_cookie_conversion_reg_cfg_be = + hal_cookie_conversion_reg_cfg_generic_be; + hal_soc->ops->hal_set_ba_aging_timeout = + hal_set_ba_aging_timeout_be_generic; }; struct hal_hw_srng_config hw_srng_table_5332[] = { @@ -2223,7 +2195,7 @@ struct hal_hw_srng_config hw_srng_table_5332[] = { }, { /* SW2WBM_RELEASE */ .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, - .max_rings = 2, + .max_rings = 1, .entry_size = sizeof(struct wbm_release_ring) >> 2, .lmac_ring = FALSE, .ring_dir = HAL_SRNG_SRC_RING, @@ -2231,12 +2203,10 @@ struct hal_hw_srng_config hw_srng_table_5332[] = { HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), }, - .reg_size = { - HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE) - - HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), - HWIO_WBM_R2_SW1_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE) - - HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE) - }, + /* Single ring - provide ring size if multiple rings of this + * type are supported + */ + .reg_size = {}, .max_size = HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, @@ -2387,58 +2357,6 @@ struct hal_hw_srng_config hw_srng_table_5332[] = { .max_size = HAL_RXDMA_MAX_RING_SIZE_BE, }, #endif - { /* REO2PPE */ - .start_ring_id = HAL_SRNG_REO2PPE, - .max_rings = 1, - .entry_size = sizeof(struct reo_destination_ring) >> 2, - .lmac_ring = FALSE, - .ring_dir = HAL_SRNG_DST_RING, - .reg_start = { - HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR( - REO_REG_REG_BASE), - HWIO_REO_R2_REO2PPE_RING_HP_ADDR( - REO_REG_REG_BASE), - }, - /* Single ring - provide ring size if multiple rings of this - * type are supported - */ - .reg_size = {}, - .max_size = - HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK >> - HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT, - }, - { /* PPE2TCL */ - .start_ring_id = HAL_SRNG_PPE2TCL1, - .max_rings = 1, - .entry_size = sizeof(struct tcl_entrance_from_ppe_ring) >> 2, - .lmac_ring = FALSE, - .ring_dir = HAL_SRNG_SRC_RING, - .reg_start = { - HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR( - MAC_TCL_REG_REG_BASE), - HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR( - MAC_TCL_REG_REG_BASE), - }, - .reg_size = {}, - .max_size = - HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> - HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, - }, - { /* PPE_RELEASE */ - .start_ring_id = HAL_SRNG_WBM_PPE_RELEASE, - .max_rings = 1, - .entry_size = sizeof(struct wbm_release_ring) >> 2, - .lmac_ring = FALSE, - .ring_dir = HAL_SRNG_SRC_RING, - .reg_start = { - HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE), - HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE), - }, - .reg_size = {}, - .max_size = - HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> - HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, - }, #ifdef QCA_MONITOR_2_0_SUPPORT { /* TX_MONITOR_BUF */ .start_ring_id = HAL_SRNG_SW2TXMON_BUF0, diff --git a/hal/wifi3.0/qca5332/hal_5332_rx.h b/hal/wifi3.0/qca5332/hal_5332_rx.h index fdb68d0e73..9b266ffa20 100644 --- a/hal/wifi3.0/qca5332/hal_5332_rx.h +++ b/hal/wifi3.0/qca5332/hal_5332_rx.h @@ -84,7 +84,7 @@ #define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \ ((struct rx_msdu_desc_info *) \ _OFFSET_TO_BYTE_PTR(msdu_details_ptr, \ -RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET)) +UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET)) #define HAL_RX_TLV_MSDU_DONE_COPY_GET(_rx_pkt_tlv) \ HAL_RX_MSDU_END(_rx_pkt_tlv).msdu_done_copy diff --git a/hal/wifi3.0/qca5332/hal_5332_tx.h b/hal/wifi3.0/qca5332/hal_5332_tx.h index 4512d6ab6d..a834016e3a 100644 --- a/hal/wifi3.0/qca5332/hal_5332_tx.h +++ b/hal/wifi3.0/qca5332/hal_5332_tx.h @@ -179,6 +179,65 @@ static void hal_tx_update_dscp_tid_5332(struct hal_soc *soc, uint8_t tid, HAL_REG_WRITE(soc, cmn_reg_addr, regval); } +#ifdef DP_TX_IMPLICIT_RBM_MAPPING + +#define RBM_MAPPING_BMSK HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK +#define RBM_MAPPING_SHFT HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT + +#define RBM_TCL_CMD_CREDIT_OFFSET \ + (HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT >> 2) + +/** + * hal_tx_config_rbm_mapping_be() - Update return buffer manager ring id + * @hal_soc: HAL SoC context + * @hal_ring_hdl: Source ring pointer + * @rbm_id: return buffer manager ring id + * + * Return: void + */ +static inline void +hal_tx_config_rbm_mapping_be_5332(hal_soc_handle_t hal_soc_hdl, + hal_ring_handle_t hal_ring_hdl, + uint8_t rbm_id) +{ + struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; + struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; + uint32_t reg_addr = 0; + uint32_t reg_val = 0; + uint32_t val = 0; + uint8_t ring_num; + enum hal_ring_type ring_type; + + ring_type = srng->ring_type; + ring_num = hal_soc->hw_srng_table[ring_type].start_ring_id; + ring_num = srng->ring_id - ring_num; + + reg_addr = HWIO_TCL_R0_RBM_MAPPING0_ADDR(MAC_TCL_REG_REG_BASE); + + if (ring_type == TCL_CMD_CREDIT) + ring_num = ring_num + RBM_TCL_CMD_CREDIT_OFFSET; + + /* get current value stored in register address */ + val = HAL_REG_READ(hal_soc, reg_addr); + + /* mask out other stored value */ + val &= (~(RBM_MAPPING_BMSK << (RBM_MAPPING_SHFT * ring_num))); + + reg_val = val | ((RBM_MAPPING_BMSK & rbm_id) << + (RBM_MAPPING_SHFT * ring_num)); + + /* write rbm mapped value to register address */ + HAL_REG_WRITE(hal_soc, reg_addr, reg_val); +} +#else +static inline void +hal_tx_config_rbm_mapping_be_5332(hal_soc_handle_t hal_soc_hdl, + hal_ring_handle_t hal_ring_hdl, + uint8_t rbm_id) +{ +} +#endif + /** * hal_tx_init_cmd_credit_ring_5332() - Initialize command/credit SRNG * @hal_soc_hdl: Handle to HAL SoC structure @@ -225,231 +284,4 @@ struct tx_fes_setup_compact_5332 { }; #endif #endif /* QCA_MONITOR_2_0_SUPPORT */ -/** - * hal_tx_set_ppe_cmn_config_5332() - Set the PPE common config register - * @hal_soc_hdl: HAL SoC handle - * @cmn_cfg: Common PPE config - * - * Based on the PPE2TCL descriptor below errors, if the below register - * values are set then the packets are forward to Tx rule handler if 1'0b - * or to TCL exit base if 1'1b. - * - * Return: void - */ -static inline -void hal_tx_set_ppe_cmn_config_5332(hal_soc_handle_t hal_soc_hdl, - union hal_tx_cmn_config_ppe *cmn_cfg) -{ - struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; - union hal_tx_cmn_config_ppe *cfg = - (union hal_tx_cmn_config_ppe *)cmn_cfg; - uint32_t reg_addr, reg_val = 0; - - reg_addr = HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(MAC_TCL_REG_REG_BASE); - - reg_val = HAL_REG_READ(soc, reg_addr); - - reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK; - reg_val |= - (cfg->drop_prec_err & - HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK) << - HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_SHFT; - - reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK; - reg_val |= - (cfg->fake_mac_hdr & - HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK) << - HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_SHFT; - - reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK; - reg_val |= - (cfg->cpu_code_inv & - HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK) << - HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_SHFT; - - reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK; - reg_val |= - (cfg->l3_l4_err & - HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK) << - HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_SHFT; - - HAL_REG_WRITE(soc, reg_addr, reg_val); -} - -/** - * hal_tx_set_ppe_vp_entry_5332() - Set the PPE VP entry - * @hal_soc_hdl: HAL SoC handle - * @vp_cfg: PPE VP config - * @ppe_vp_idx : PPE VP index to the table - * - * Return: void - */ -static inline -void hal_tx_set_ppe_vp_entry_5332(hal_soc_handle_t hal_soc_hdl, - union hal_tx_ppe_vp_config *cfg, - int ppe_vp_idx) -{ - struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; - uint32_t reg_addr, reg_val = 0; - - reg_addr = HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE, - ppe_vp_idx); - - /* - * Drop precedence is enabled by default. - */ - reg_val = HAL_REG_READ(soc, reg_addr); - - reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VP_NUM_BMSK; - reg_val |= (cfg->vp_num & - HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VP_NUM_BMSK) << - HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VP_NUM_SHFT; - - reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PMAC_ID_BMSK; - reg_val |= (cfg->pmac_id & - HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PMAC_ID_BMSK) << - HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_PMAC_ID_SHFT; - - reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_BANK_ID_BMSK; - reg_val |= (cfg->bank_id & - HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_BANK_ID_BMSK) << - HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_BANK_ID_SHFT; - - reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VDEV_ID_BMSK; - reg_val |= (cfg->vdev_id & - HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VDEV_ID_BMSK) << - HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_VDEV_ID_SHFT; - - reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_SEARCH_INDEX_REG_NUM_BMSK; - reg_val |= - (cfg->search_idx_reg_num & - HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_SEARCH_INDEX_REG_NUM_BMSK) << - HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_SEARCH_INDEX_REG_NUM_SHFT; - - reg_val &= - ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK; - reg_val |= - (cfg->use_ppe_int_pri & - HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK) << - HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_SHFT; - - reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_TO_FW_BMSK; - reg_val |= (cfg->to_fw & - HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_TO_FW_BMSK) << - HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_TO_FW_SHFT; - - reg_val &= ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_DROP_PREC_ENABLE_BMSK; - reg_val |= (cfg->drop_prec_enable & - HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_DROP_PREC_ENABLE_BMSK) << - HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_DROP_PREC_ENABLE_SHFT; - - HAL_REG_WRITE(soc, reg_addr, reg_val); -} - -/** - * hal_tx_set_ppe_pri2tid_map1_5332() - * @hal_soc_hdl: HAL SoC handle - * @val : PRI to TID value - * @map_no: Map number - * - * Return: void - */ -static inline -void hal_tx_set_ppe_pri2tid_map_5332(hal_soc_handle_t hal_soc_hdl, - uint32_t val, uint8_t map_no) -{ - struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; - uint32_t reg_addr, reg_val = 0; - - if (map_no == 0) - reg_addr = - HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(MAC_TCL_REG_REG_BASE); - else - reg_addr = - HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(MAC_TCL_REG_REG_BASE); - - reg_val |= val; - HAL_REG_WRITE(soc, reg_addr, reg_val); -} - -/** - * hal_tx_set_ppe_pri2tid_map1_5332() - * @hal_soc_hdl: HAL SoC handle - * @val : PRI to TID value - * @map_no: Map number - * - * Return: void - */ -static inline -void hal_tx_enable_pri2tid_map_5332(hal_soc_handle_t hal_soc_hdl, - bool val, uint8_t ppe_vp_idx) -{ - struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; - uint32_t reg_addr, reg_val = 0; - - reg_addr = HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE, - ppe_vp_idx); - - /* - * Drop precedence is enabled by default. - */ - reg_val = HAL_REG_READ(soc, reg_addr); - - reg_val &= - ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK; - - reg_val |= - (val & - HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK) << - HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_SHFT; - - HAL_REG_WRITE(soc, reg_addr, reg_val); -} - -/** - * hal_tx_update_ppe_pri2tid_5332() - * @hal_soc_hdl: HAL SoC handle - * @pri: INT_PRI - * @tid: Wi-Fi TID - * - * Return: void - */ -static inline -void hal_tx_update_ppe_pri2tid_5332(hal_soc_handle_t hal_soc_hdl, - uint8_t pri, uint8_t tid) -{ - struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; - uint32_t reg_addr, reg_val = 0, mask, shift; - - /* - * INT_PRI 0..9 is in MAP0 register and INT_PRI 10..15 - * is in MAP1 register. - */ - switch (pri) { - case 0 ... 9: - reg_addr = - HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(MAC_TCL_REG_REG_BASE); - mask = - (HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_BMSK << (0x3 * pri)); - shift = HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_SHFT + (pri * 0x3); - break; - case 10 ... 15: - pri = pri - 10; - reg_addr = - HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(MAC_TCL_REG_REG_BASE); - mask = - (HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_BMSK << (0x3 * pri)); - shift = - HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_SHFT + (pri * 0x3); - break; - default: - return; - } - - reg_val = HAL_REG_READ(soc, reg_addr); - reg_val &= ~mask; - reg_val |= (pri << shift) & mask; - - HAL_REG_WRITE(soc, reg_addr, reg_val); -} #endif /* _HAL_5332_TX_H_ */ diff --git a/hal/wifi3.0/qcn9224/hal_9224.c b/hal/wifi3.0/qcn9224/hal_9224.c index 689130144d..d5b27a51b3 100644 --- a/hal/wifi3.0/qcn9224/hal_9224.c +++ b/hal/wifi3.0/qcn9224/hal_9224.c @@ -1753,6 +1753,8 @@ static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc) hal_tx_get_num_ppe_vp_tbl_entries_9224; hal_soc->ops->hal_tx_enable_pri2tid_map = hal_tx_enable_pri2tid_map_9224; + hal_soc->ops->hal_tx_config_rbm_mapping_be = + hal_tx_config_rbm_mapping_be_9224; /* rx */ hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be; @@ -1965,6 +1967,18 @@ static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc) hal_txmon_status_free_buffer_generic_be; #endif /* QCA_MONITOR_2_0_SUPPORT */ hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; + hal_soc->ops->hal_tx_vdev_mismatch_routing_set = + hal_tx_vdev_mismatch_routing_set_generic_be; + hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set = + hal_tx_mcast_mlo_reinject_routing_set_generic_be; + hal_soc->ops->hal_get_ba_aging_timeout = + hal_get_ba_aging_timeout_be_generic; + hal_soc->ops->hal_setup_link_idle_list = + hal_setup_link_idle_list_generic_be; + hal_soc->ops->hal_cookie_conversion_reg_cfg_be = + hal_cookie_conversion_reg_cfg_generic_be; + hal_soc->ops->hal_set_ba_aging_timeout = + hal_set_ba_aging_timeout_be_generic; }; struct hal_hw_srng_config hw_srng_table_9224[] = { diff --git a/hal/wifi3.0/qcn9224/hal_9224_tx.h b/hal/wifi3.0/qcn9224/hal_9224_tx.h index d67a9852c1..5f0dac69a9 100644 --- a/hal/wifi3.0/qcn9224/hal_9224_tx.h +++ b/hal/wifi3.0/qcn9224/hal_9224_tx.h @@ -181,6 +181,69 @@ static void hal_tx_update_dscp_tid_9224(struct hal_soc *soc, uint8_t tid, HAL_REG_WRITE(soc, cmn_reg_addr, regval); } +#ifdef DP_TX_IMPLICIT_RBM_MAPPING + +#define RBM_MAPPING_BMSK HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK +#define RBM_MAPPING_SHFT HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT + +#define RBM_PPE2TCL_OFFSET \ + (HWIO_TCL_R0_RBM_MAPPING0_PPE2TCL1_RING_SHFT >> 2) +#define RBM_TCL_CMD_CREDIT_OFFSET \ + (HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT >> 2) + +/** + * hal_tx_config_rbm_mapping_be() - Update return buffer manager ring id + * @hal_soc: HAL SoC context + * @hal_ring_hdl: Source ring pointer + * @rbm_id: return buffer manager ring id + * + * Return: void + */ +static inline void +hal_tx_config_rbm_mapping_be_9224(hal_soc_handle_t hal_soc_hdl, + hal_ring_handle_t hal_ring_hdl, + uint8_t rbm_id) +{ + struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; + struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; + uint32_t reg_addr = 0; + uint32_t reg_val = 0; + uint32_t val = 0; + uint8_t ring_num; + enum hal_ring_type ring_type; + + ring_type = srng->ring_type; + ring_num = hal_soc->hw_srng_table[ring_type].start_ring_id; + ring_num = srng->ring_id - ring_num; + + reg_addr = HWIO_TCL_R0_RBM_MAPPING0_ADDR(MAC_TCL_REG_REG_BASE); + + if (ring_type == PPE2TCL) + ring_num = ring_num + RBM_PPE2TCL_OFFSET; + else if (ring_type == TCL_CMD_CREDIT) + ring_num = ring_num + RBM_TCL_CMD_CREDIT_OFFSET; + + /* get current value stored in register address */ + val = HAL_REG_READ(hal_soc, reg_addr); + + /* mask out other stored value */ + val &= (~(RBM_MAPPING_BMSK << (RBM_MAPPING_SHFT * ring_num))); + + reg_val = val | ((RBM_MAPPING_BMSK & rbm_id) << + (RBM_MAPPING_SHFT * ring_num)); + + /* write rbm mapped value to register address */ + HAL_REG_WRITE(hal_soc, reg_addr, reg_val); +} +#else +static inline void +hal_tx_config_rbm_mapping_be_9224(hal_soc_handle_t hal_soc_hdl, + hal_ring_handle_t hal_ring_hdl, + uint8_t rbm_id) +{ +} +#endif + /** * hal_tx_init_cmd_credit_ring_9224() - Initialize command/credit SRNG * @hal_soc_hdl: Handle to HAL SoC structure