qcacmn: Hal related changes for QCA5332
1. Changes to move hal_tx_config_rbm_mapping_be function from common to device specific as it has ppe related snippets. 2. Changes to remove all PPE related codes in QCA5332 hal code. 3. Changes to correct macros according to fw_hrs. 4. Changes to move functions with device specific Macros to header files so that it gets compiled with respective device's FW headers and gets correct Macros Change-Id: I479b406f318aa42d2b1032349aaf42d95b8c18e5 CRs-Fixed: 3235966
This commit is contained in:
Hariharan Ramanathan
committed by
Madan Koyyalamudi
Madan Koyyalamudi
parent
7e799fcbae
commit
16630d2422
@@ -296,155 +296,6 @@ static uint8_t hal_get_wbm_internal_error_generic_be(void *hal_desc)
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HAL_WBM_INTERNAL_ERROR_LSB;
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}
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/**
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* hal_setup_link_idle_list_generic_be - Setup scattered idle list using the
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* buffer list provided
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*
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* @hal_soc: Opaque HAL SOC handle
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* @scatter_bufs_base_paddr: Array of physical base addresses
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* @scatter_bufs_base_vaddr: Array of virtual base addresses
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* @num_scatter_bufs: Number of scatter buffers in the above lists
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* @scatter_buf_size: Size of each scatter buffer
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* @last_buf_end_offset: Offset to the last entry
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* @num_entries: Total entries of all scatter bufs
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*
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* Return: None
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*/
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static void
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hal_setup_link_idle_list_generic_be(struct hal_soc *soc,
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qdf_dma_addr_t scatter_bufs_base_paddr[],
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void *scatter_bufs_base_vaddr[],
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uint32_t num_scatter_bufs,
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uint32_t scatter_buf_size,
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uint32_t last_buf_end_offset,
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uint32_t num_entries)
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{
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int i;
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uint32_t *prev_buf_link_ptr = NULL;
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uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size;
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uint32_t val;
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/* Link the scatter buffers */
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for (i = 0; i < num_scatter_bufs; i++) {
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if (i > 0) {
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prev_buf_link_ptr[0] =
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scatter_bufs_base_paddr[i] & 0xffffffff;
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prev_buf_link_ptr[1] = HAL_SM(
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HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
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BASE_ADDRESS_39_32,
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((uint64_t)(scatter_bufs_base_paddr[i])
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>> 32)) | HAL_SM(
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HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
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ADDRESS_MATCH_TAG,
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ADDRESS_MATCH_TAG_VAL);
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}
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prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] +
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scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE);
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}
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/* TBD: Register programming partly based on MLD & the rest based on
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* inputs from HW team. Not complete yet.
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*/
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reg_scatter_buf_size = (scatter_buf_size -
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WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) / 64;
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reg_tot_scatter_buf_size = ((scatter_buf_size -
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WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs) / 64;
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(
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WBM_REG_REG_BASE),
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HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, SCATTER_BUFFER_SIZE,
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reg_scatter_buf_size) |
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HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, LINK_DESC_IDLE_LIST_MODE,
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0x1));
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(
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WBM_REG_REG_BASE),
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HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE,
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SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST,
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reg_tot_scatter_buf_size));
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(
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WBM_REG_REG_BASE),
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scatter_bufs_base_paddr[0] & 0xffffffff);
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(
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WBM_REG_REG_BASE),
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((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) &
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HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK);
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(
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WBM_REG_REG_BASE),
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HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
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BASE_ADDRESS_39_32, ((uint64_t)(scatter_bufs_base_paddr[0])
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>> 32)) |
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HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB,
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ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL));
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/* ADDRESS_MATCH_TAG field in the above register is expected to match
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* with the upper bits of link pointer. The above write sets this field
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* to zero and we are also setting the upper bits of link pointers to
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* zero while setting up the link list of scatter buffers above
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*/
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/* Setup head and tail pointers for the idle list */
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(
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WBM_REG_REG_BASE),
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scatter_bufs_base_paddr[num_scatter_bufs - 1] & 0xffffffff);
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(
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WBM_REG_REG_BASE),
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HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
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BUFFER_ADDRESS_39_32,
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((uint64_t)(scatter_bufs_base_paddr[num_scatter_bufs - 1])
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>> 32)) |
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HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1,
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HEAD_POINTER_OFFSET, last_buf_end_offset >> 2));
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(
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WBM_REG_REG_BASE),
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scatter_bufs_base_paddr[0] & 0xffffffff);
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(
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WBM_REG_REG_BASE),
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scatter_bufs_base_paddr[0] & 0xffffffff);
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(
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WBM_REG_REG_BASE),
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HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
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BUFFER_ADDRESS_39_32,
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((uint64_t)(scatter_bufs_base_paddr[0]) >>
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32)) | HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1,
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TAIL_POINTER_OFFSET, 0));
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(
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WBM_REG_REG_BASE),
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2 * num_entries);
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/* Set RING_ID_DISABLE */
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val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1);
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/*
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* SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence
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* check the presence of the bit before toggling it.
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*/
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#ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK
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val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1);
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#endif
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HAL_REG_WRITE(soc,
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HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(WBM_REG_REG_BASE),
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val);
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}
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/**
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* hal_rx_wbm_err_src_get_be() - Get WBM error source from descriptor
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* @ring_desc: ring descriptor
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@@ -757,125 +608,9 @@ static uint8_t hal_rx_reo_buf_type_get_be(hal_ring_desc_t rx_desc)
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void hal_cookie_conversion_reg_cfg_be(hal_soc_handle_t hal_soc_hdl,
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struct hal_hw_cc_config *cc_cfg)
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{
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uint32_t reg_addr, reg_val = 0;
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struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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/* REO CFG */
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reg_addr = HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(REO_REG_REG_BASE);
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reg_val = cc_cfg->lut_base_addr_31_0;
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HAL_REG_WRITE(soc, reg_addr, reg_val);
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reg_addr = HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(REO_REG_REG_BASE);
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reg_val = 0;
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reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
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SW_COOKIE_CONVERT_GLOBAL_ENABLE,
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cc_cfg->cc_global_en);
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reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
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SW_COOKIE_CONVERT_ENABLE,
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cc_cfg->cc_global_en);
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reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
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PAGE_ALIGNMENT,
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cc_cfg->page_4k_align);
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reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
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COOKIE_OFFSET_MSB,
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cc_cfg->cookie_offset_msb);
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reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
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COOKIE_PAGE_MSB,
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cc_cfg->cookie_page_msb);
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reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1,
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CMEM_LUT_BASE_ADDR_39_32,
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cc_cfg->lut_base_addr_39_32);
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HAL_REG_WRITE(soc, reg_addr, reg_val);
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/* WBM CFG */
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reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(WBM_REG_REG_BASE);
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reg_val = cc_cfg->lut_base_addr_31_0;
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HAL_REG_WRITE(soc, reg_addr, reg_val);
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reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(WBM_REG_REG_BASE);
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reg_val = 0;
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
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PAGE_ALIGNMENT,
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cc_cfg->page_4k_align);
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
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COOKIE_OFFSET_MSB,
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cc_cfg->cookie_offset_msb);
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
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COOKIE_PAGE_MSB,
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cc_cfg->cookie_page_msb);
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1,
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CMEM_LUT_BASE_ADDR_39_32,
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cc_cfg->lut_base_addr_39_32);
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HAL_REG_WRITE(soc, reg_addr, reg_val);
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/*
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* WCSS_UMAC_WBM_R0_SW_COOKIE_CONVERT_CFG default value is 0x1FE,
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*/
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reg_addr = HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(WBM_REG_REG_BASE);
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reg_val = 0;
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
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WBM_COOKIE_CONV_GLOBAL_ENABLE,
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cc_cfg->cc_global_en);
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
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WBM2SW6_COOKIE_CONVERSION_EN,
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cc_cfg->wbm2sw6_cc_en);
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
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WBM2SW5_COOKIE_CONVERSION_EN,
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cc_cfg->wbm2sw5_cc_en);
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
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WBM2SW4_COOKIE_CONVERSION_EN,
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cc_cfg->wbm2sw4_cc_en);
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
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WBM2SW3_COOKIE_CONVERSION_EN,
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cc_cfg->wbm2sw3_cc_en);
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
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WBM2SW2_COOKIE_CONVERSION_EN,
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cc_cfg->wbm2sw2_cc_en);
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
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WBM2SW1_COOKIE_CONVERSION_EN,
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cc_cfg->wbm2sw1_cc_en);
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
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WBM2SW0_COOKIE_CONVERSION_EN,
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cc_cfg->wbm2sw0_cc_en);
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reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG,
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WBM2FW_COOKIE_CONVERSION_EN,
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cc_cfg->wbm2fw_cc_en);
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HAL_REG_WRITE(soc, reg_addr, reg_val);
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#ifdef HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK
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reg_addr = HWIO_WBM_R0_WBM_CFG_2_ADDR(WBM_REG_REG_BASE);
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reg_val = 0;
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reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
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COOKIE_DEBUG_SEL,
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cc_cfg->cc_global_en);
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reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
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COOKIE_CONV_INDICATION_EN,
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cc_cfg->cc_global_en);
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reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
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ERROR_PATH_COOKIE_CONV_EN,
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cc_cfg->error_path_cookie_conv_en);
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reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2,
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RELEASE_PATH_COOKIE_CONV_EN,
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cc_cfg->release_path_cookie_conv_en);
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HAL_REG_WRITE(soc, reg_addr, reg_val);
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#endif
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#ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
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/*
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* To enable indication for HW cookie conversion done or not for
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* WBM, WCSS_UMAC_WBM_R0_MISC_CONTROL spare_control field 15th
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* bit spare_control[15] should be set.
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*/
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reg_addr = HWIO_WBM_R0_MISC_CONTROL_ADDR(WBM_REG_REG_BASE);
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reg_val = HAL_REG_READ(soc, reg_addr);
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reg_val |= HAL_SM(HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL,
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SPARE_CONTROL,
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HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15);
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HAL_REG_WRITE(soc, reg_addr, reg_val);
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#endif
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hal_soc->ops->hal_cookie_conversion_reg_cfg_be(hal_soc_hdl, cc_cfg);
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}
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qdf_export_symbol(hal_cookie_conversion_reg_cfg_be);
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@@ -1053,14 +788,9 @@ void hal_hw_txrx_default_ops_attach_be(struct hal_soc *hal_soc)
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hal_soc->ops->hal_get_rx_max_ba_window = hal_get_rx_max_ba_window_be;
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hal_soc->ops->hal_set_link_desc_addr = hal_set_link_desc_addr_be;
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hal_soc->ops->hal_tx_init_data_ring = hal_tx_init_data_ring_be;
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hal_soc->ops->hal_get_ba_aging_timeout = hal_get_ba_aging_timeout_be;
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hal_soc->ops->hal_set_ba_aging_timeout = hal_set_ba_aging_timeout_be;
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hal_soc->ops->hal_get_reo_reg_base_offset =
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hal_get_reo_reg_base_offset_be;
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hal_soc->ops->hal_setup_link_idle_list =
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hal_setup_link_idle_list_generic_be;
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hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_be;
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hal_soc->ops->hal_rx_reo_buf_paddr_get = hal_rx_reo_buf_paddr_get_be;
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hal_soc->ops->hal_rx_msdu_link_desc_set = hal_rx_msdu_link_desc_set_be;
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hal_soc->ops->hal_rx_buf_cookie_rbm_get = hal_rx_buf_cookie_rbm_get_be;
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