disp: msm: dsi: rework DSI PLL to be configured within PHY

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Change avoids clock framework APIs to configure the DSI PHY
PLL. It follows HW recommendation to set the byte and pclk
dividers.

Change-Id: I8c110f3997e4ec4c2eaa28778b70091855725ab8
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>

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Satya Rama Aditya Pinapala

2020-01-25 14:25:11 -08:00

parent 819630e6b0

commit 0a93edbae6

16 changed files with 1176 additions and 4197 deletions

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msm/dsi/dsi_pll_5nm.c

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