disp: msm: dsi: rework DSI PLL to be configured within PHY

Change avoids clock framework APIs to configure the DSI PHY
PLL. It follows HW recommendation to set the byte and pclk
dividers.

Change-Id: I8c110f3997e4ec4c2eaa28778b70091855725ab8
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>

msm/dsi/dsi_defs.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _DSI_DEFS_H_
@@ -739,6 +739,23 @@ static inline int dsi_pixel_format_to_bpp(enum dsi_pixel_format fmt)
 	return 24;
 }
 
+/* return number of DSI data lanes */
+static inline int dsi_get_num_of_data_lanes(enum dsi_data_lanes dlanes)
+{
+	int num_of_lanes = 0;
+
+	if (dlanes & DSI_DATA_LANE_0)
+		num_of_lanes++;
+	if (dlanes & DSI_DATA_LANE_1)
+		num_of_lanes++;
+	if (dlanes & DSI_DATA_LANE_2)
+		num_of_lanes++;
+	if (dlanes & DSI_DATA_LANE_3)
+		num_of_lanes++;
+
+	return num_of_lanes;
+}
+
 static inline u64 dsi_h_active_dce(struct dsi_mode_info *mode)
 {
 	u64 h_active = 0;