disp: msm: dsi: rework DSI PLL to be configured within PHY

Change avoids clock framework APIs to configure the DSI PHY
PLL. It follows HW recommendation to set the byte and pclk
dividers.

Change-Id: I8c110f3997e4ec4c2eaa28778b70091855725ab8
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>

msm/dsi/dsi_catalog.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
  */
 
 #include <linux/errno.h>
@@ -343,3 +343,26 @@ int dsi_catalog_phy_setup(struct dsi_phy_hw *phy,
 
 	return rc;
 }
+
+int dsi_catalog_phy_pll_setup(struct dsi_phy_hw *phy, u32 pll_ver)
+{
+	int rc = 0;
+
+	if (pll_ver >= DSI_PLL_VERSION_UNKNOWN) {
+		DSI_ERR("Unsupported version: %d\n", pll_ver);
+		return -EOPNOTSUPP;
+	}
+
+	switch (pll_ver) {
+	case DSI_PLL_VERSION_5NM:
+		phy->ops.configure = dsi_pll_5nm_configure;
+		phy->ops.pll_toggle = dsi_pll_5nm_toggle;
+		break;
+	default:
+		phy->ops.configure = NULL;
+		phy->ops.pll_toggle = NULL;
+		break;
+	}
+
+	return rc;
+}