qcacmn: Add default register values for WCN6450
Add default register values required for WCN6450. Change-Id: I47880e95cb101ad145d4e750e8811a0153b19482 CRs-Fixed: 3381090
This commit is contained in:
Venkateswara Naralasetty
committed by
Madan Koyyalamudi
Madan Koyyalamudi
parent
cef49bdf89
commit
06e90b5374
@@ -489,6 +489,12 @@ struct host_shadow_regs_s {
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* @d_HOST_IE_COPY_COMPLETE_MASK: Bits indicating Copy complete interrupt
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* enable from the IE register
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*
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* @d_HOST_IE_SRC_TIMER_BATCH_MASK: Bits indicating src timer batch interrupt
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* enable from the IE register
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*
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* @d_HOST_IE_DST_TIMER_BATCH_MASK: Bits indicating dst timer batch interrupt
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* enable from the IE register
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*
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* @d_SR_BA_ADDRESS: LSB of Source Ring Base Address
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*
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* @d_SR_BA_ADDRESS_HIGH: MSB of Source Ring Base Address
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@@ -590,6 +596,24 @@ struct host_shadow_regs_s {
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*
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* @d_HOST_CMEM_ADDRESS: Base address of CMEM
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*
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* @d_CE_SRC_BATCH_TIMER_THRESH_MASK: SRC ring timer threshold for interrupt
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*
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* @d_CE_SRC_BATCH_COUNTER_THRESH_MASK: SRC ring counter threshold for
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* interrupt
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*
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* @d_CE_SRC_BATCH_TIMER_THRESH_LSB: LSB for src ring timer threshold
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*
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* @d_CE_SRC_BATCH_COUNTER_THRESH_LSB: LSB for src ring counter threshold
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*
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* @d_CE_DST_BATCH_TIMER_THRESH_MASK: DST ring timer threshold for interrupt
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*
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* @d_CE_DST_BATCH_COUNTER_THRESH_MASK: DST ring counter threshold for
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* interrupt
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*
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* @d_CE_DST_BATCH_TIMER_THRESH_LSB: LSB for dst ring timer threshold
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*
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* @d_CE_DST_BATCH_COUNTER_THRESH_LSB: LSB for dst ring counter threshold
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*
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*/
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struct ce_reg_def {
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/* copy_engine.c */
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@@ -615,6 +639,8 @@ struct ce_reg_def {
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uint32_t d_HOST_IE_ADDRESS;
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uint32_t d_HOST_IE_ADDRESS_2;
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uint32_t d_HOST_IE_COPY_COMPLETE_MASK;
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uint32_t d_HOST_IE_SRC_TIMER_BATCH_MASK;
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uint32_t d_HOST_IE_DST_TIMER_BATCH_MASK;
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uint32_t d_SR_BA_ADDRESS;
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uint32_t d_SR_BA_ADDRESS_HIGH;
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uint32_t d_SR_SIZE_ADDRESS;
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@@ -666,6 +692,16 @@ struct ce_reg_def {
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uint32_t d_HOST_CE_ADDRESS;
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uint32_t d_HOST_CMEM_ADDRESS;
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uint32_t d_PMM_SCRATCH_BASE;
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uint32_t d_CE_SRC_BATCH_TIMER_THRESH_MASK;
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uint32_t d_CE_SRC_BATCH_COUNTER_THRESH_MASK;
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uint32_t d_CE_SRC_BATCH_TIMER_THRESH_LSB;
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uint32_t d_CE_SRC_BATCH_COUNTER_THRESH_LSB;
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uint32_t d_CE_DST_BATCH_TIMER_THRESH_MASK;
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uint32_t d_CE_DST_BATCH_COUNTER_THRESH_MASK;
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uint32_t d_CE_DST_BATCH_TIMER_THRESH_LSB;
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uint32_t d_CE_DST_BATCH_COUNTER_THRESH_LSB;
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uint32_t d_CE_SRC_BATCH_TIMER_INT_SETUP;
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uint32_t d_CE_DST_BATCH_TIMER_INT_SETUP;
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};
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#endif
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382
hif/src/wcn6450def.h
Normal file
382
hif/src/wcn6450def.h
Normal file
@@ -0,0 +1,382 @@
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#if defined(WCN6450_HEADERS_DEF)
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#include "msmhwiobase.h"
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#include "hwio.h"
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#define WCN6450_CE0_BASE_ADDRESS HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE
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#define WCN6450_CE1_BASE_ADDRESS HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE
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#define WCN6450_SR_WR_INDEX_OFFSET \
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(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR - \
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WCN6450_CE0_BASE_ADDRESS)
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#define WCN6450_DST_WR_INDEX_OFFSET \
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(HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR - \
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WCN6450_CE0_BASE_ADDRESS)
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#define WCN6450_SRC_WATERMARK_OFFSET \
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(HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR - \
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WCN6450_CE0_BASE_ADDRESS)
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#define WCN6450_SRC_WATERMARK_LOW_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_BMSK
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#define WCN6450_SRC_WATERMARK_LOW_LSB \
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HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_SHFT
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#define WCN6450_SRC_WATERMARK_HIGH_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_BMSK
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#define WCN6450_SRC_WATERMARK_HIGH_LSB \
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HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_SHFT
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#define WCN6450_DST_WATERMARK_OFFSET \
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(HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR - \
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WCN6450_CE0_BASE_ADDRESS)
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#define WCN6450_DST_WATERMARK_LOW_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_BMSK
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#define WCN6450_DST_WATERMARK_LOW_LSB \
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HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_SHFT
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#define WCN6450_DST_WATERMARK_HIGH_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_BMSK
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#define WCN6450_DST_WATERMARK_HIGH_LSB \
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HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_SHFT
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#define WCN6450_CURRENT_SRRI_OFFSET \
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(HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_ADDR - \
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WCN6450_CE0_BASE_ADDRESS)
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#define WCN6450_CURRENT_DRRI_OFFSET \
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(HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_ADDR - \
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WCN6450_CE0_BASE_ADDRESS)
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#define WCN6450_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_HIGH_WATERMARK_BMSK
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#define WCN6450_HOST_IS_SRC_RING_LOW_WATERMARK_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_LOW_WATERMARK_BMSK
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#define WCN6450_HOST_IS_DST_RING_HIGH_WATERMARK_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_HIGH_WATERMARK_BMSK
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#define WCN6450_HOST_IS_DST_RING_LOW_WATERMARK_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_LOW_WATERMARK_BMSK
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#define WCN6450_HOST_IS_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR \
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- WCN6450_CE0_BASE_ADDRESS)
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#define WCN6450_MISC_IS_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR \
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- WCN6450_CE0_BASE_ADDRESS)
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#define WCN6450_HOST_IS_COPY_COMPLETE_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_COPY_COMPLETE_BMSK
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#define WCN6450_CE_COMMON_WRAPPER_BASE_ADDRESS \
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HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE
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#define WCN6450_CE_COMMON_WRAPPER_INTERRUPT_SUMMARY_ADDRESS_OFFSET \
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(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_ADDR \
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- WCN6450_CE_COMMON_WRAPPER_BASE_ADDRESS)
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#define WCN6450_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \
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HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_HOST_BMSK
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#define WCN6450_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \
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HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_HOST_SHFT
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#define WCN6450_CE_DDR_ADDRESS_FOR_RRI_LOW \
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(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR \
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- WCN6450_CE_COMMON_WRAPPER_BASE_ADDRESS)
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#define WCN6450_CE_DDR_ADDRESS_FOR_RRI_HIGH \
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(HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR \
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- WCN6450_CE_COMMON_WRAPPER_BASE_ADDRESS)
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#define WCN6450_HOST_IE_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR \
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- WCN6450_CE0_BASE_ADDRESS)
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#define WCN6450_HOST_IE_COPY_COMPLETE_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_COPY_COMPLETE_BMSK
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#define WCN6450_HOST_IE_SRC_BATCH_TIMER_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_TIMER_BATCH_BMSK
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#define WCN6450_HOST_IE_DST_BATCH_TIMER_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_TIMER_BATCH_BMSK
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#define WCN6450_SR_BA_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR \
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- WCN6450_CE0_BASE_ADDRESS)
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#define WCN6450_SR_BA_HIGH_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR \
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- WCN6450_CE0_BASE_ADDRESS)
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#define WCN6450_SR_SIZE_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR \
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- WCN6450_CE0_BASE_ADDRESS)
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#define WCN6450_DR_BA_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR \
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- WCN6450_CE0_BASE_ADDRESS)
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#define WCN6450_DR_BA_HIGH_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR \
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- WCN6450_CE0_BASE_ADDRESS)
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#define WCN6450_DR_SIZE_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR \
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- WCN6450_CE0_BASE_ADDRESS)
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#define WCN6450_CE_CTRL1_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR \
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- WCN6450_CE0_BASE_ADDRESS)
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#define WCN6450_CE_CTRL1_DMAX_LENGTH_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DEST_MAX_LENGTH_BMSK
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#define WCN6450_CE_CTRL1_DMAX_LENGTH_LSB \
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HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DEST_MAX_LENGTH_SHFT
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#define WCN6450_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_BMSK
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#define WCN6450_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB \
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HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SHFT
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#define WCN6450_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DST_RING_BYTE_SWAP_EN_BMSK
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#define WCN6450_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB \
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HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DST_RING_BYTE_SWAP_EN_SHFT
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#define WCN6450_CE_CTRL1_IDX_UPD_EN_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_IDX_UPD_EN_BMSK
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#define WCN6450_CE_CMD_REGISTER_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR \
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- WCN6450_CE0_BASE_ADDRESS)
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#define WCN6450_CE_MSI_ADDRESS \
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(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR - \
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WCN6450_CE0_BASE_ADDRESS)
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#define WCN6450_CE_MSI_ADDRESS_HIGH \
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(HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR - \
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WCN6450_CE0_BASE_ADDRESS)
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#define WCN6450_CE_MSI_DATA (HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR \
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- WCN6450_CE0_BASE_ADDRESS)
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#define WCN6450_CE_MSI_ENABLE_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_HOST_MSI_EN_BMSK
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#define WCN6450_CE_SRC_BATCH_TIMER_THRESH_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK
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#define WCN6450_CE_SRC_BATCH_COUNTER_THRESH_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK
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#define WCN6450_CE_SRC_BATCH_TIMER_THRESH_LSB \
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HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT
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#define WCN6450_CE_SRC_BATCH_COUNTER_THRESH_LSB \
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HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT
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#define WCN6450_CE_SRC_BATCH_TIMER_INT_SETUP_OFFSET \
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(HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR \
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- WCN6450_CE0_BASE_ADDRESS)
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#define WCN6450_CE_DST_BATCH_TIMER_THRESH_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK
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#define WCN6450_CE_DST_BATCH_COUNTER_THRESH_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK
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#define WCN6450_CE_DST_BATCH_TIMER_THRESH_LSB \
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HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT
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#define WCN6450_CE_DST_BATCH_COUNTER_THRESH_LSB \
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HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT
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#define WCN6450_CE_DST_BATCH_TIMER_INT_SETUP_OFFSET \
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(HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR \
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- WCN6450_CE0_BASE_ADDRESS)
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#define WCN6450_MISC_IE_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR \
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- WCN6450_CE0_BASE_ADDRESS)
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#define WCN6450_MISC_IS_AXI_ERR_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_AXI_BUS_ERR_BMSK
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#define WCN6450_MISC_IS_SRC_LEN_ERR_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_LEN_ERR_BMSK
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#define WCN6450_MISC_IS_DST_MAX_LEN_VIO_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_MAX_LEN_VIO_BMSK
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#define WCN6450_MISC_IS_DST_RING_OVERFLOW_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_OVERFLOW_BMSK
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#define WCN6450_MISC_IS_SRC_RING_OVERFLOW_MASK \
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HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_OVERFLOW_BMSK
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#define WCN6450_MISC_IS_DST_ADDR_ERR_MASK MISSING
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#define WCN6450_CE_WRAPPER_DEBUG_OFFSET MISSING
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#define WCN6450_CE_WRAPPER_DEBUG_SEL_MSB MISSING
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#define WCN6450_CE_WRAPPER_DEBUG_SEL_LSB MISSING
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#define WCN6450_CE_WRAPPER_DEBUG_SEL_MASK MISSING
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#define WCN6450_CE_DEBUG_OFFSET MISSING
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#define WCN6450_CE_DEBUG_SEL_MSB MISSING
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#define WCN6450_CE_DEBUG_SEL_LSB MISSING
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#define WCN6450_CE_DEBUG_SEL_MASK MISSING
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#define MISSING_FOR_WCN6450 MISSING
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#define WCN6450_CE_COUNT 12
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#define SHADOW_REG_VAL_START_OFFSET 0x00000504
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#define SHADOW_REGISTER_VAL(x) ((SHADOW_REG_VAL_START_OFFSET) + (4 * (x)))
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#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_0 SHADOW_REGISTER_VAL(0)
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#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_1 SHADOW_REGISTER_VAL(1)
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#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_2 SHADOW_REGISTER_VAL(2)
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#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_3 SHADOW_REGISTER_VAL(3)
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#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_4 SHADOW_REGISTER_VAL(4)
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#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_5 SHADOW_REGISTER_VAL(5)
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#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_6 SHADOW_REGISTER_VAL(6)
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#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_7 SHADOW_REGISTER_VAL(7)
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#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_8 SHADOW_REGISTER_VAL(8)
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#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_9 SHADOW_REGISTER_VAL(9)
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#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_10 SHADOW_REGISTER_VAL(10)
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#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_11 SHADOW_REGISTER_VAL(11)
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#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_12 SHADOW_REGISTER_VAL(12)
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#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_13 SHADOW_REGISTER_VAL(13)
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#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_14 SHADOW_REGISTER_VAL(14)
|
||||
#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_15 SHADOW_REGISTER_VAL(15)
|
||||
#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_16 SHADOW_REGISTER_VAL(16)
|
||||
#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_17 SHADOW_REGISTER_VAL(17)
|
||||
#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_18 SHADOW_REGISTER_VAL(18)
|
||||
#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_19 SHADOW_REGISTER_VAL(19)
|
||||
#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_20 SHADOW_REGISTER_VAL(20)
|
||||
#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_21 SHADOW_REGISTER_VAL(21)
|
||||
#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_22 SHADOW_REGISTER_VAL(22)
|
||||
#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_23 SHADOW_REGISTER_VAL(23)
|
||||
|
||||
struct targetdef_s wcn6450_targetdef = {
|
||||
.d_FW_INDICATOR_ADDRESS = MISSING_FOR_WCN6450,
|
||||
.d_SR_WR_INDEX_ADDRESS = WCN6450_SR_WR_INDEX_OFFSET,
|
||||
.d_DST_WATERMARK_ADDRESS = WCN6450_DST_WATERMARK_OFFSET,
|
||||
.d_CE_COUNT = WCN6450_CE_COUNT,
|
||||
};
|
||||
|
||||
struct hostdef_s wcn6450_hostdef = {
|
||||
.d_HOST_CE_COUNT = WCN6450_CE_COUNT,
|
||||
.d_MUX_ID_MASK = 0xf000,
|
||||
.d_TRANSACTION_ID_MASK = 0x0fff,
|
||||
.d_DESC_DATA_FLAG_MASK = 0x7FFF1F00,
|
||||
};
|
||||
|
||||
struct ce_reg_def wcn6450_ce_targetdef = {
|
||||
.d_DST_WR_INDEX_ADDRESS = WCN6450_DST_WR_INDEX_OFFSET,
|
||||
.d_SRC_WATERMARK_ADDRESS = WCN6450_SRC_WATERMARK_OFFSET,
|
||||
.d_SRC_WATERMARK_LOW_MASK = WCN6450_SRC_WATERMARK_LOW_MASK,
|
||||
.d_SRC_WATERMARK_HIGH_MASK = WCN6450_SRC_WATERMARK_HIGH_MASK,
|
||||
.d_DST_WATERMARK_LOW_MASK = WCN6450_DST_WATERMARK_LOW_MASK,
|
||||
.d_DST_WATERMARK_HIGH_MASK = WCN6450_DST_WATERMARK_HIGH_MASK,
|
||||
.d_CURRENT_SRRI_ADDRESS = WCN6450_CURRENT_SRRI_OFFSET,
|
||||
.d_CURRENT_DRRI_ADDRESS = WCN6450_CURRENT_DRRI_OFFSET,
|
||||
.d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK =
|
||||
WCN6450_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK,
|
||||
.d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK =
|
||||
WCN6450_HOST_IS_SRC_RING_LOW_WATERMARK_MASK,
|
||||
.d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK =
|
||||
WCN6450_HOST_IS_DST_RING_HIGH_WATERMARK_MASK,
|
||||
.d_HOST_IS_DST_RING_LOW_WATERMARK_MASK =
|
||||
WCN6450_HOST_IS_DST_RING_LOW_WATERMARK_MASK,
|
||||
.d_HOST_IS_ADDRESS = WCN6450_HOST_IS_OFFSET,
|
||||
.d_MISC_IS_ADDRESS = WCN6450_MISC_IS_OFFSET,
|
||||
.d_HOST_IS_COPY_COMPLETE_MASK = WCN6450_HOST_IS_COPY_COMPLETE_MASK,
|
||||
.d_CE_WRAPPER_BASE_ADDRESS = WCN6450_CE_COMMON_WRAPPER_BASE_ADDRESS,
|
||||
.d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS =
|
||||
WCN6450_CE_COMMON_WRAPPER_INTERRUPT_SUMMARY_ADDRESS_OFFSET,
|
||||
.d_CE_DDR_ADDRESS_FOR_RRI_LOW =
|
||||
WCN6450_CE_DDR_ADDRESS_FOR_RRI_LOW,
|
||||
.d_CE_DDR_ADDRESS_FOR_RRI_HIGH =
|
||||
WCN6450_CE_DDR_ADDRESS_FOR_RRI_HIGH,
|
||||
.d_HOST_IE_ADDRESS = WCN6450_HOST_IE_OFFSET,
|
||||
.d_HOST_IE_COPY_COMPLETE_MASK = WCN6450_HOST_IE_COPY_COMPLETE_MASK,
|
||||
.d_HOST_IE_SRC_TIMER_BATCH_MASK = WCN6450_HOST_IE_SRC_BATCH_TIMER_MASK,
|
||||
.d_HOST_IE_DST_TIMER_BATCH_MASK = WCN6450_HOST_IE_DST_BATCH_TIMER_MASK,
|
||||
.d_SR_BA_ADDRESS = WCN6450_SR_BA_OFFSET,
|
||||
.d_SR_BA_ADDRESS_HIGH = WCN6450_SR_BA_HIGH_OFFSET,
|
||||
.d_SR_SIZE_ADDRESS = WCN6450_SR_SIZE_OFFSET,
|
||||
.d_CE_CTRL1_ADDRESS = WCN6450_CE_CTRL1_OFFSET,
|
||||
.d_CE_CTRL1_DMAX_LENGTH_MASK = WCN6450_CE_CTRL1_DMAX_LENGTH_MASK,
|
||||
.d_DR_BA_ADDRESS = WCN6450_DR_BA_OFFSET,
|
||||
.d_DR_BA_ADDRESS_HIGH = WCN6450_DR_BA_HIGH_OFFSET,
|
||||
.d_DR_SIZE_ADDRESS = WCN6450_DR_SIZE_OFFSET,
|
||||
.d_CE_CMD_REGISTER = WCN6450_CE_CMD_REGISTER_OFFSET,
|
||||
.d_CE_MSI_ADDRESS = WCN6450_CE_MSI_ADDRESS,
|
||||
.d_CE_MSI_ADDRESS_HIGH = WCN6450_CE_MSI_ADDRESS_HIGH,
|
||||
.d_CE_MSI_DATA = WCN6450_CE_MSI_DATA,
|
||||
.d_CE_MSI_ENABLE_BIT = WCN6450_CE_MSI_ENABLE_MASK,
|
||||
.d_MISC_IE_ADDRESS = WCN6450_MISC_IE_OFFSET,
|
||||
.d_MISC_IS_AXI_ERR_MASK = WCN6450_MISC_IS_AXI_ERR_MASK,
|
||||
.d_MISC_IS_DST_ADDR_ERR_MASK = WCN6450_MISC_IS_DST_ADDR_ERR_MASK,
|
||||
.d_MISC_IS_SRC_LEN_ERR_MASK = WCN6450_MISC_IS_SRC_LEN_ERR_MASK,
|
||||
.d_MISC_IS_DST_MAX_LEN_VIO_MASK = WCN6450_MISC_IS_DST_MAX_LEN_VIO_MASK,
|
||||
.d_MISC_IS_DST_RING_OVERFLOW_MASK =
|
||||
WCN6450_MISC_IS_DST_RING_OVERFLOW_MASK,
|
||||
.d_MISC_IS_SRC_RING_OVERFLOW_MASK =
|
||||
WCN6450_MISC_IS_SRC_RING_OVERFLOW_MASK,
|
||||
.d_SRC_WATERMARK_LOW_LSB = WCN6450_SRC_WATERMARK_LOW_LSB,
|
||||
.d_SRC_WATERMARK_HIGH_LSB = WCN6450_SRC_WATERMARK_HIGH_LSB,
|
||||
.d_DST_WATERMARK_LOW_LSB = WCN6450_DST_WATERMARK_LOW_LSB,
|
||||
.d_DST_WATERMARK_HIGH_LSB = WCN6450_DST_WATERMARK_HIGH_LSB,
|
||||
.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK =
|
||||
WCN6450_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK,
|
||||
.d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB =
|
||||
WCN6450_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB,
|
||||
.d_CE_CTRL1_DMAX_LENGTH_LSB = WCN6450_CE_CTRL1_DMAX_LENGTH_LSB,
|
||||
.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK =
|
||||
WCN6450_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK,
|
||||
.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK =
|
||||
WCN6450_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK,
|
||||
.d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB =
|
||||
WCN6450_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB,
|
||||
.d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB =
|
||||
WCN6450_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB,
|
||||
.d_CE_CTRL1_IDX_UPD_EN_MASK = WCN6450_CE_CTRL1_IDX_UPD_EN_MASK,
|
||||
.d_CE_WRAPPER_DEBUG_OFFSET = WCN6450_CE_WRAPPER_DEBUG_OFFSET,
|
||||
.d_CE_WRAPPER_DEBUG_SEL_MSB = WCN6450_CE_WRAPPER_DEBUG_SEL_MSB,
|
||||
.d_CE_WRAPPER_DEBUG_SEL_LSB = WCN6450_CE_WRAPPER_DEBUG_SEL_LSB,
|
||||
.d_CE_WRAPPER_DEBUG_SEL_MASK = WCN6450_CE_WRAPPER_DEBUG_SEL_MASK,
|
||||
.d_CE_DEBUG_OFFSET = WCN6450_CE_DEBUG_OFFSET,
|
||||
.d_CE_DEBUG_SEL_MSB = WCN6450_CE_DEBUG_SEL_MSB,
|
||||
.d_CE_DEBUG_SEL_LSB = WCN6450_CE_DEBUG_SEL_LSB,
|
||||
.d_CE_DEBUG_SEL_MASK = WCN6450_CE_DEBUG_SEL_MASK,
|
||||
.d_CE0_BASE_ADDRESS = WCN6450_CE0_BASE_ADDRESS,
|
||||
.d_CE1_BASE_ADDRESS = WCN6450_CE1_BASE_ADDRESS,
|
||||
.d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES =
|
||||
MISSING_FOR_WCN6450,
|
||||
.d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS =
|
||||
MISSING_FOR_WCN6450,
|
||||
.d_CE_SRC_BATCH_TIMER_THRESH_MASK =
|
||||
WCN6450_CE_SRC_BATCH_TIMER_THRESH_MASK,
|
||||
.d_CE_SRC_BATCH_COUNTER_THRESH_MASK =
|
||||
WCN6450_CE_SRC_BATCH_COUNTER_THRESH_MASK,
|
||||
.d_CE_SRC_BATCH_TIMER_THRESH_LSB =
|
||||
WCN6450_CE_SRC_BATCH_TIMER_THRESH_LSB,
|
||||
.d_CE_SRC_BATCH_COUNTER_THRESH_LSB =
|
||||
WCN6450_CE_SRC_BATCH_COUNTER_THRESH_LSB,
|
||||
.d_CE_DST_BATCH_TIMER_THRESH_MASK =
|
||||
WCN6450_CE_DST_BATCH_TIMER_THRESH_MASK,
|
||||
.d_CE_DST_BATCH_COUNTER_THRESH_MASK =
|
||||
WCN6450_CE_DST_BATCH_COUNTER_THRESH_MASK,
|
||||
.d_CE_DST_BATCH_TIMER_THRESH_LSB =
|
||||
WCN6450_CE_DST_BATCH_TIMER_THRESH_LSB,
|
||||
.d_CE_DST_BATCH_COUNTER_THRESH_LSB =
|
||||
WCN6450_CE_DST_BATCH_COUNTER_THRESH_LSB,
|
||||
.d_CE_SRC_BATCH_TIMER_INT_SETUP =
|
||||
WCN6450_CE_SRC_BATCH_TIMER_INT_SETUP_OFFSET,
|
||||
.d_CE_DST_BATCH_TIMER_INT_SETUP =
|
||||
WCN6450_CE_DST_BATCH_TIMER_INT_SETUP_OFFSET,
|
||||
};
|
||||
|
||||
struct host_shadow_regs_s wcn6450_host_shadow_regs = {
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_0 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_0,
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_1 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_1,
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_2 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_2,
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_3 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_3,
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_4 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_4,
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_5 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_5,
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_6 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_6,
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_7 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_7,
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_8 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_8,
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_9 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_9,
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_10 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_10,
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_11 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_11,
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_12 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_12,
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_13 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_13,
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_14 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_14,
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_15 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_15,
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_16 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_16,
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_17 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_17,
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_18 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_18,
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_19 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_19,
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_20 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_20,
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_21 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_21,
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_22 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_22,
|
||||
.d_A_LOCAL_SHADOW_REG_VALUE_23 =
|
||||
WCN6450_A_LOCAL_SHADOW_REG_VALUE_23,
|
||||
};
|
||||
#endif
|
||||
Reference in New Issue
Block a user