diff --git a/hif/inc/reg_struct.h b/hif/inc/reg_struct.h index e09bd3fab2..c2be154fde 100644 --- a/hif/inc/reg_struct.h +++ b/hif/inc/reg_struct.h @@ -489,6 +489,12 @@ struct host_shadow_regs_s { * @d_HOST_IE_COPY_COMPLETE_MASK: Bits indicating Copy complete interrupt * enable from the IE register * + * @d_HOST_IE_SRC_TIMER_BATCH_MASK: Bits indicating src timer batch interrupt + * enable from the IE register + * + * @d_HOST_IE_DST_TIMER_BATCH_MASK: Bits indicating dst timer batch interrupt + * enable from the IE register + * * @d_SR_BA_ADDRESS: LSB of Source Ring Base Address * * @d_SR_BA_ADDRESS_HIGH: MSB of Source Ring Base Address @@ -590,6 +596,24 @@ struct host_shadow_regs_s { * * @d_HOST_CMEM_ADDRESS: Base address of CMEM * + * @d_CE_SRC_BATCH_TIMER_THRESH_MASK: SRC ring timer threshold for interrupt + * + * @d_CE_SRC_BATCH_COUNTER_THRESH_MASK: SRC ring counter threshold for + * interrupt + * + * @d_CE_SRC_BATCH_TIMER_THRESH_LSB: LSB for src ring timer threshold + * + * @d_CE_SRC_BATCH_COUNTER_THRESH_LSB: LSB for src ring counter threshold + * + * @d_CE_DST_BATCH_TIMER_THRESH_MASK: DST ring timer threshold for interrupt + * + * @d_CE_DST_BATCH_COUNTER_THRESH_MASK: DST ring counter threshold for + * interrupt + * + * @d_CE_DST_BATCH_TIMER_THRESH_LSB: LSB for dst ring timer threshold + * + * @d_CE_DST_BATCH_COUNTER_THRESH_LSB: LSB for dst ring counter threshold + * */ struct ce_reg_def { /* copy_engine.c */ @@ -615,6 +639,8 @@ struct ce_reg_def { uint32_t d_HOST_IE_ADDRESS; uint32_t d_HOST_IE_ADDRESS_2; uint32_t d_HOST_IE_COPY_COMPLETE_MASK; + uint32_t d_HOST_IE_SRC_TIMER_BATCH_MASK; + uint32_t d_HOST_IE_DST_TIMER_BATCH_MASK; uint32_t d_SR_BA_ADDRESS; uint32_t d_SR_BA_ADDRESS_HIGH; uint32_t d_SR_SIZE_ADDRESS; @@ -666,6 +692,16 @@ struct ce_reg_def { uint32_t d_HOST_CE_ADDRESS; uint32_t d_HOST_CMEM_ADDRESS; uint32_t d_PMM_SCRATCH_BASE; + uint32_t d_CE_SRC_BATCH_TIMER_THRESH_MASK; + uint32_t d_CE_SRC_BATCH_COUNTER_THRESH_MASK; + uint32_t d_CE_SRC_BATCH_TIMER_THRESH_LSB; + uint32_t d_CE_SRC_BATCH_COUNTER_THRESH_LSB; + uint32_t d_CE_DST_BATCH_TIMER_THRESH_MASK; + uint32_t d_CE_DST_BATCH_COUNTER_THRESH_MASK; + uint32_t d_CE_DST_BATCH_TIMER_THRESH_LSB; + uint32_t d_CE_DST_BATCH_COUNTER_THRESH_LSB; + uint32_t d_CE_SRC_BATCH_TIMER_INT_SETUP; + uint32_t d_CE_DST_BATCH_TIMER_INT_SETUP; }; #endif diff --git a/hif/src/wcn6450def.h b/hif/src/wcn6450def.h new file mode 100644 index 0000000000..90e3ded089 --- /dev/null +++ b/hif/src/wcn6450def.h @@ -0,0 +1,382 @@ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#if defined(WCN6450_HEADERS_DEF) + +#include "msmhwiobase.h" +#include "hwio.h" + +#define WCN6450_CE0_BASE_ADDRESS HOST_SOC_A_WFSS_CE0_WFSS_CE_0_REG_REG_BASE +#define WCN6450_CE1_BASE_ADDRESS HOST_SOC_A_WFSS_CE1_WFSS_CE_1_REG_REG_BASE + +#define WCN6450_SR_WR_INDEX_OFFSET \ + (HWIO_HOST_SOC_A_WFSS_CE0_SRC_WR_INDEX_ADDR - \ + WCN6450_CE0_BASE_ADDRESS) +#define WCN6450_DST_WR_INDEX_OFFSET \ + (HWIO_HOST_SOC_A_WFSS_CE0_DST_WR_INDEX_ADDR - \ + WCN6450_CE0_BASE_ADDRESS) +#define WCN6450_SRC_WATERMARK_OFFSET \ + (HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_ADDR - \ + WCN6450_CE0_BASE_ADDRESS) +#define WCN6450_SRC_WATERMARK_LOW_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_BMSK +#define WCN6450_SRC_WATERMARK_LOW_LSB \ + HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_LOW_WATER_MARK_THRESOLD_SHFT +#define WCN6450_SRC_WATERMARK_HIGH_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_BMSK +#define WCN6450_SRC_WATERMARK_HIGH_LSB \ + HWIO_HOST_SOC_A_WFSS_CE0_SRC_WATERMARK_SR_HIGH_WATER_MARK_THRESHOLD_SHFT +#define WCN6450_DST_WATERMARK_OFFSET \ + (HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_ADDR - \ + WCN6450_CE0_BASE_ADDRESS) +#define WCN6450_DST_WATERMARK_LOW_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_BMSK +#define WCN6450_DST_WATERMARK_LOW_LSB \ + HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_LOW_WATER_MARK_THRESHOLD_SHFT +#define WCN6450_DST_WATERMARK_HIGH_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_BMSK +#define WCN6450_DST_WATERMARK_HIGH_LSB \ + HWIO_HOST_SOC_A_WFSS_CE0_DST_WATERMARK_DR_HIGH_WATER_MARK_THRESHOLD_SHFT +#define WCN6450_CURRENT_SRRI_OFFSET \ + (HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_SRRI_ADDR - \ + WCN6450_CE0_BASE_ADDRESS) +#define WCN6450_CURRENT_DRRI_OFFSET \ + (HWIO_HOST_SOC_A_WFSS_CE0_CURRENT_DRRI_ADDR - \ + WCN6450_CE0_BASE_ADDRESS) +#define WCN6450_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_HIGH_WATERMARK_BMSK +#define WCN6450_HOST_IS_SRC_RING_LOW_WATERMARK_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_SRC_RING_LOW_WATERMARK_BMSK +#define WCN6450_HOST_IS_DST_RING_HIGH_WATERMARK_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_HIGH_WATERMARK_BMSK +#define WCN6450_HOST_IS_DST_RING_LOW_WATERMARK_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_DST_RING_LOW_WATERMARK_BMSK +#define WCN6450_HOST_IS_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_ADDR \ + - WCN6450_CE0_BASE_ADDRESS) +#define WCN6450_MISC_IS_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR \ + - WCN6450_CE0_BASE_ADDRESS) +#define WCN6450_HOST_IS_COPY_COMPLETE_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_HOST_IS_COPY_COMPLETE_BMSK +#define WCN6450_CE_COMMON_WRAPPER_BASE_ADDRESS \ + HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_REG_BASE +#define WCN6450_CE_COMMON_WRAPPER_INTERRUPT_SUMMARY_ADDRESS_OFFSET \ + (HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_ADDR \ + - WCN6450_CE_COMMON_WRAPPER_BASE_ADDRESS) +#define WCN6450_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \ + HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_HOST_BMSK +#define WCN6450_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \ + HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_HOST_INTERRUPT_SUMMARY_HOST_SHFT +#define WCN6450_CE_DDR_ADDRESS_FOR_RRI_LOW \ + (HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_LOW_ADDR \ + - WCN6450_CE_COMMON_WRAPPER_BASE_ADDRESS) +#define WCN6450_CE_DDR_ADDRESS_FOR_RRI_HIGH \ + (HWIO_HOST_SOC_A_WFSS_CE_COMMON_WRAPPER_CE_WRAPPER_INDEX_BASE_HIGH_ADDR \ + - WCN6450_CE_COMMON_WRAPPER_BASE_ADDRESS) +#define WCN6450_HOST_IE_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_ADDR \ + - WCN6450_CE0_BASE_ADDRESS) +#define WCN6450_HOST_IE_COPY_COMPLETE_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_COPY_COMPLETE_BMSK +#define WCN6450_HOST_IE_SRC_BATCH_TIMER_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_SRC_TIMER_BATCH_BMSK +#define WCN6450_HOST_IE_DST_BATCH_TIMER_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_HOST_IE_DST_TIMER_BATCH_BMSK +#define WCN6450_SR_BA_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_LOW_ADDR \ + - WCN6450_CE0_BASE_ADDRESS) +#define WCN6450_SR_BA_HIGH_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_SR_BA_HIGH_ADDR \ + - WCN6450_CE0_BASE_ADDRESS) +#define WCN6450_SR_SIZE_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_SR_SIZE_ADDR \ + - WCN6450_CE0_BASE_ADDRESS) +#define WCN6450_DR_BA_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_LOW_ADDR \ + - WCN6450_CE0_BASE_ADDRESS) +#define WCN6450_DR_BA_HIGH_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_DR_BA_HIGH_ADDR \ + - WCN6450_CE0_BASE_ADDRESS) +#define WCN6450_DR_SIZE_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_DR_SIZE_ADDR \ + - WCN6450_CE0_BASE_ADDRESS) +#define WCN6450_CE_CTRL1_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_ADDR \ + - WCN6450_CE0_BASE_ADDRESS) +#define WCN6450_CE_CTRL1_DMAX_LENGTH_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DEST_MAX_LENGTH_BMSK +#define WCN6450_CE_CTRL1_DMAX_LENGTH_LSB \ + HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DEST_MAX_LENGTH_SHFT +#define WCN6450_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_BMSK +#define WCN6450_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB \ + HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SHFT +#define WCN6450_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DST_RING_BYTE_SWAP_EN_BMSK +#define WCN6450_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB \ + HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_DST_RING_BYTE_SWAP_EN_SHFT +#define WCN6450_CE_CTRL1_IDX_UPD_EN_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_IDX_UPD_EN_BMSK +#define WCN6450_CE_CMD_REGISTER_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_CE_CMD_ADDR \ + - WCN6450_CE0_BASE_ADDRESS) +#define WCN6450_CE_MSI_ADDRESS \ + (HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_LOW_ADDR - \ + WCN6450_CE0_BASE_ADDRESS) +#define WCN6450_CE_MSI_ADDRESS_HIGH \ + (HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_ADDR_HIGH_ADDR - \ + WCN6450_CE0_BASE_ADDRESS) +#define WCN6450_CE_MSI_DATA (HWIO_HOST_SOC_A_WFSS_CE0_HOST_MSI_DATA_ADDR \ + - WCN6450_CE0_BASE_ADDRESS) +#define WCN6450_CE_MSI_ENABLE_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_CE_CTRL1_HOST_MSI_EN_BMSK +#define WCN6450_CE_SRC_BATCH_TIMER_THRESH_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK +#define WCN6450_CE_SRC_BATCH_COUNTER_THRESH_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK +#define WCN6450_CE_SRC_BATCH_TIMER_THRESH_LSB \ + HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT +#define WCN6450_CE_SRC_BATCH_COUNTER_THRESH_LSB \ + HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT +#define WCN6450_CE_SRC_BATCH_TIMER_INT_SETUP_OFFSET \ + (HWIO_HOST_SOC_A_WFSS_CE0_CE_SRC_BATCH_TIMER_INT_SETUP_ADDR \ + - WCN6450_CE0_BASE_ADDRESS) +#define WCN6450_CE_DST_BATCH_TIMER_THRESH_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK +#define WCN6450_CE_DST_BATCH_COUNTER_THRESH_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK +#define WCN6450_CE_DST_BATCH_TIMER_THRESH_LSB \ + HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT +#define WCN6450_CE_DST_BATCH_COUNTER_THRESH_LSB \ + HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT +#define WCN6450_CE_DST_BATCH_TIMER_INT_SETUP_OFFSET \ + (HWIO_HOST_SOC_A_WFSS_CE0_CE_DST_BATCH_TIMER_INT_SETUP_ADDR \ + - WCN6450_CE0_BASE_ADDRESS) +#define WCN6450_MISC_IE_OFFSET (HWIO_HOST_SOC_A_WFSS_CE0_MISC_IE_ADDR \ + - WCN6450_CE0_BASE_ADDRESS) +#define WCN6450_MISC_IS_AXI_ERR_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_AXI_BUS_ERR_BMSK +#define WCN6450_MISC_IS_SRC_LEN_ERR_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_LEN_ERR_BMSK +#define WCN6450_MISC_IS_DST_MAX_LEN_VIO_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_MAX_LEN_VIO_BMSK +#define WCN6450_MISC_IS_DST_RING_OVERFLOW_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_DST_RING_OVERFLOW_BMSK +#define WCN6450_MISC_IS_SRC_RING_OVERFLOW_MASK \ + HWIO_HOST_SOC_A_WFSS_CE0_MISC_IS_SRC_RING_OVERFLOW_BMSK + +#define WCN6450_MISC_IS_DST_ADDR_ERR_MASK MISSING +#define WCN6450_CE_WRAPPER_DEBUG_OFFSET MISSING +#define WCN6450_CE_WRAPPER_DEBUG_SEL_MSB MISSING +#define WCN6450_CE_WRAPPER_DEBUG_SEL_LSB MISSING +#define WCN6450_CE_WRAPPER_DEBUG_SEL_MASK MISSING +#define WCN6450_CE_DEBUG_OFFSET MISSING +#define WCN6450_CE_DEBUG_SEL_MSB MISSING +#define WCN6450_CE_DEBUG_SEL_LSB MISSING +#define WCN6450_CE_DEBUG_SEL_MASK MISSING +#define MISSING_FOR_WCN6450 MISSING +#define WCN6450_CE_COUNT 12 + +#define SHADOW_REG_VAL_START_OFFSET 0x00000504 +#define SHADOW_REGISTER_VAL(x) ((SHADOW_REG_VAL_START_OFFSET) + (4 * (x))) + +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_0 SHADOW_REGISTER_VAL(0) +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_1 SHADOW_REGISTER_VAL(1) +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_2 SHADOW_REGISTER_VAL(2) +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_3 SHADOW_REGISTER_VAL(3) +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_4 SHADOW_REGISTER_VAL(4) +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_5 SHADOW_REGISTER_VAL(5) +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_6 SHADOW_REGISTER_VAL(6) +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_7 SHADOW_REGISTER_VAL(7) +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_8 SHADOW_REGISTER_VAL(8) +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_9 SHADOW_REGISTER_VAL(9) +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_10 SHADOW_REGISTER_VAL(10) +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_11 SHADOW_REGISTER_VAL(11) +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_12 SHADOW_REGISTER_VAL(12) +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_13 SHADOW_REGISTER_VAL(13) +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_14 SHADOW_REGISTER_VAL(14) +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_15 SHADOW_REGISTER_VAL(15) +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_16 SHADOW_REGISTER_VAL(16) +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_17 SHADOW_REGISTER_VAL(17) +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_18 SHADOW_REGISTER_VAL(18) +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_19 SHADOW_REGISTER_VAL(19) +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_20 SHADOW_REGISTER_VAL(20) +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_21 SHADOW_REGISTER_VAL(21) +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_22 SHADOW_REGISTER_VAL(22) +#define WCN6450_A_LOCAL_SHADOW_REG_VALUE_23 SHADOW_REGISTER_VAL(23) + +struct targetdef_s wcn6450_targetdef = { + .d_FW_INDICATOR_ADDRESS = MISSING_FOR_WCN6450, + .d_SR_WR_INDEX_ADDRESS = WCN6450_SR_WR_INDEX_OFFSET, + .d_DST_WATERMARK_ADDRESS = WCN6450_DST_WATERMARK_OFFSET, + .d_CE_COUNT = WCN6450_CE_COUNT, +}; + +struct hostdef_s wcn6450_hostdef = { + .d_HOST_CE_COUNT = WCN6450_CE_COUNT, + .d_MUX_ID_MASK = 0xf000, + .d_TRANSACTION_ID_MASK = 0x0fff, + .d_DESC_DATA_FLAG_MASK = 0x7FFF1F00, +}; + +struct ce_reg_def wcn6450_ce_targetdef = { + .d_DST_WR_INDEX_ADDRESS = WCN6450_DST_WR_INDEX_OFFSET, + .d_SRC_WATERMARK_ADDRESS = WCN6450_SRC_WATERMARK_OFFSET, + .d_SRC_WATERMARK_LOW_MASK = WCN6450_SRC_WATERMARK_LOW_MASK, + .d_SRC_WATERMARK_HIGH_MASK = WCN6450_SRC_WATERMARK_HIGH_MASK, + .d_DST_WATERMARK_LOW_MASK = WCN6450_DST_WATERMARK_LOW_MASK, + .d_DST_WATERMARK_HIGH_MASK = WCN6450_DST_WATERMARK_HIGH_MASK, + .d_CURRENT_SRRI_ADDRESS = WCN6450_CURRENT_SRRI_OFFSET, + .d_CURRENT_DRRI_ADDRESS = WCN6450_CURRENT_DRRI_OFFSET, + .d_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK = + WCN6450_HOST_IS_SRC_RING_HIGH_WATERMARK_MASK, + .d_HOST_IS_SRC_RING_LOW_WATERMARK_MASK = + WCN6450_HOST_IS_SRC_RING_LOW_WATERMARK_MASK, + .d_HOST_IS_DST_RING_HIGH_WATERMARK_MASK = + WCN6450_HOST_IS_DST_RING_HIGH_WATERMARK_MASK, + .d_HOST_IS_DST_RING_LOW_WATERMARK_MASK = + WCN6450_HOST_IS_DST_RING_LOW_WATERMARK_MASK, + .d_HOST_IS_ADDRESS = WCN6450_HOST_IS_OFFSET, + .d_MISC_IS_ADDRESS = WCN6450_MISC_IS_OFFSET, + .d_HOST_IS_COPY_COMPLETE_MASK = WCN6450_HOST_IS_COPY_COMPLETE_MASK, + .d_CE_WRAPPER_BASE_ADDRESS = WCN6450_CE_COMMON_WRAPPER_BASE_ADDRESS, + .d_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS = + WCN6450_CE_COMMON_WRAPPER_INTERRUPT_SUMMARY_ADDRESS_OFFSET, + .d_CE_DDR_ADDRESS_FOR_RRI_LOW = + WCN6450_CE_DDR_ADDRESS_FOR_RRI_LOW, + .d_CE_DDR_ADDRESS_FOR_RRI_HIGH = + WCN6450_CE_DDR_ADDRESS_FOR_RRI_HIGH, + .d_HOST_IE_ADDRESS = WCN6450_HOST_IE_OFFSET, + .d_HOST_IE_COPY_COMPLETE_MASK = WCN6450_HOST_IE_COPY_COMPLETE_MASK, + .d_HOST_IE_SRC_TIMER_BATCH_MASK = WCN6450_HOST_IE_SRC_BATCH_TIMER_MASK, + .d_HOST_IE_DST_TIMER_BATCH_MASK = WCN6450_HOST_IE_DST_BATCH_TIMER_MASK, + .d_SR_BA_ADDRESS = WCN6450_SR_BA_OFFSET, + .d_SR_BA_ADDRESS_HIGH = WCN6450_SR_BA_HIGH_OFFSET, + .d_SR_SIZE_ADDRESS = WCN6450_SR_SIZE_OFFSET, + .d_CE_CTRL1_ADDRESS = WCN6450_CE_CTRL1_OFFSET, + .d_CE_CTRL1_DMAX_LENGTH_MASK = WCN6450_CE_CTRL1_DMAX_LENGTH_MASK, + .d_DR_BA_ADDRESS = WCN6450_DR_BA_OFFSET, + .d_DR_BA_ADDRESS_HIGH = WCN6450_DR_BA_HIGH_OFFSET, + .d_DR_SIZE_ADDRESS = WCN6450_DR_SIZE_OFFSET, + .d_CE_CMD_REGISTER = WCN6450_CE_CMD_REGISTER_OFFSET, + .d_CE_MSI_ADDRESS = WCN6450_CE_MSI_ADDRESS, + .d_CE_MSI_ADDRESS_HIGH = WCN6450_CE_MSI_ADDRESS_HIGH, + .d_CE_MSI_DATA = WCN6450_CE_MSI_DATA, + .d_CE_MSI_ENABLE_BIT = WCN6450_CE_MSI_ENABLE_MASK, + .d_MISC_IE_ADDRESS = WCN6450_MISC_IE_OFFSET, + .d_MISC_IS_AXI_ERR_MASK = WCN6450_MISC_IS_AXI_ERR_MASK, + .d_MISC_IS_DST_ADDR_ERR_MASK = WCN6450_MISC_IS_DST_ADDR_ERR_MASK, + .d_MISC_IS_SRC_LEN_ERR_MASK = WCN6450_MISC_IS_SRC_LEN_ERR_MASK, + .d_MISC_IS_DST_MAX_LEN_VIO_MASK = WCN6450_MISC_IS_DST_MAX_LEN_VIO_MASK, + .d_MISC_IS_DST_RING_OVERFLOW_MASK = + WCN6450_MISC_IS_DST_RING_OVERFLOW_MASK, + .d_MISC_IS_SRC_RING_OVERFLOW_MASK = + WCN6450_MISC_IS_SRC_RING_OVERFLOW_MASK, + .d_SRC_WATERMARK_LOW_LSB = WCN6450_SRC_WATERMARK_LOW_LSB, + .d_SRC_WATERMARK_HIGH_LSB = WCN6450_SRC_WATERMARK_HIGH_LSB, + .d_DST_WATERMARK_LOW_LSB = WCN6450_DST_WATERMARK_LOW_LSB, + .d_DST_WATERMARK_HIGH_LSB = WCN6450_DST_WATERMARK_HIGH_LSB, + .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK = + WCN6450_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK, + .d_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB = + WCN6450_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB, + .d_CE_CTRL1_DMAX_LENGTH_LSB = WCN6450_CE_CTRL1_DMAX_LENGTH_LSB, + .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK = + WCN6450_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK, + .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK = + WCN6450_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK, + .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB = + WCN6450_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB, + .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB = + WCN6450_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB, + .d_CE_CTRL1_IDX_UPD_EN_MASK = WCN6450_CE_CTRL1_IDX_UPD_EN_MASK, + .d_CE_WRAPPER_DEBUG_OFFSET = WCN6450_CE_WRAPPER_DEBUG_OFFSET, + .d_CE_WRAPPER_DEBUG_SEL_MSB = WCN6450_CE_WRAPPER_DEBUG_SEL_MSB, + .d_CE_WRAPPER_DEBUG_SEL_LSB = WCN6450_CE_WRAPPER_DEBUG_SEL_LSB, + .d_CE_WRAPPER_DEBUG_SEL_MASK = WCN6450_CE_WRAPPER_DEBUG_SEL_MASK, + .d_CE_DEBUG_OFFSET = WCN6450_CE_DEBUG_OFFSET, + .d_CE_DEBUG_SEL_MSB = WCN6450_CE_DEBUG_SEL_MSB, + .d_CE_DEBUG_SEL_LSB = WCN6450_CE_DEBUG_SEL_LSB, + .d_CE_DEBUG_SEL_MASK = WCN6450_CE_DEBUG_SEL_MASK, + .d_CE0_BASE_ADDRESS = WCN6450_CE0_BASE_ADDRESS, + .d_CE1_BASE_ADDRESS = WCN6450_CE1_BASE_ADDRESS, + .d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES = + MISSING_FOR_WCN6450, + .d_A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS = + MISSING_FOR_WCN6450, + .d_CE_SRC_BATCH_TIMER_THRESH_MASK = + WCN6450_CE_SRC_BATCH_TIMER_THRESH_MASK, + .d_CE_SRC_BATCH_COUNTER_THRESH_MASK = + WCN6450_CE_SRC_BATCH_COUNTER_THRESH_MASK, + .d_CE_SRC_BATCH_TIMER_THRESH_LSB = + WCN6450_CE_SRC_BATCH_TIMER_THRESH_LSB, + .d_CE_SRC_BATCH_COUNTER_THRESH_LSB = + WCN6450_CE_SRC_BATCH_COUNTER_THRESH_LSB, + .d_CE_DST_BATCH_TIMER_THRESH_MASK = + WCN6450_CE_DST_BATCH_TIMER_THRESH_MASK, + .d_CE_DST_BATCH_COUNTER_THRESH_MASK = + WCN6450_CE_DST_BATCH_COUNTER_THRESH_MASK, + .d_CE_DST_BATCH_TIMER_THRESH_LSB = + WCN6450_CE_DST_BATCH_TIMER_THRESH_LSB, + .d_CE_DST_BATCH_COUNTER_THRESH_LSB = + WCN6450_CE_DST_BATCH_COUNTER_THRESH_LSB, + .d_CE_SRC_BATCH_TIMER_INT_SETUP = + WCN6450_CE_SRC_BATCH_TIMER_INT_SETUP_OFFSET, + .d_CE_DST_BATCH_TIMER_INT_SETUP = + WCN6450_CE_DST_BATCH_TIMER_INT_SETUP_OFFSET, +}; + +struct host_shadow_regs_s wcn6450_host_shadow_regs = { + .d_A_LOCAL_SHADOW_REG_VALUE_0 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_0, + .d_A_LOCAL_SHADOW_REG_VALUE_1 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_1, + .d_A_LOCAL_SHADOW_REG_VALUE_2 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_2, + .d_A_LOCAL_SHADOW_REG_VALUE_3 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_3, + .d_A_LOCAL_SHADOW_REG_VALUE_4 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_4, + .d_A_LOCAL_SHADOW_REG_VALUE_5 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_5, + .d_A_LOCAL_SHADOW_REG_VALUE_6 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_6, + .d_A_LOCAL_SHADOW_REG_VALUE_7 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_7, + .d_A_LOCAL_SHADOW_REG_VALUE_8 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_8, + .d_A_LOCAL_SHADOW_REG_VALUE_9 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_9, + .d_A_LOCAL_SHADOW_REG_VALUE_10 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_10, + .d_A_LOCAL_SHADOW_REG_VALUE_11 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_11, + .d_A_LOCAL_SHADOW_REG_VALUE_12 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_12, + .d_A_LOCAL_SHADOW_REG_VALUE_13 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_13, + .d_A_LOCAL_SHADOW_REG_VALUE_14 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_14, + .d_A_LOCAL_SHADOW_REG_VALUE_15 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_15, + .d_A_LOCAL_SHADOW_REG_VALUE_16 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_16, + .d_A_LOCAL_SHADOW_REG_VALUE_17 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_17, + .d_A_LOCAL_SHADOW_REG_VALUE_18 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_18, + .d_A_LOCAL_SHADOW_REG_VALUE_19 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_19, + .d_A_LOCAL_SHADOW_REG_VALUE_20 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_20, + .d_A_LOCAL_SHADOW_REG_VALUE_21 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_21, + .d_A_LOCAL_SHADOW_REG_VALUE_22 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_22, + .d_A_LOCAL_SHADOW_REG_VALUE_23 = + WCN6450_A_LOCAL_SHADOW_REG_VALUE_23, +}; +#endif