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ff0e2a7bd13f7c332d7f09ff45d08df4bf512ce0
android_kernel_xiaomi_sm8450/arch/riscv/include/asm
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Anup Patel ff0e2a7bd1 RISC-V: Fix FIXMAP_TOP to avoid overlap with VMALLOC area 
The FIXMAP area overlaps with VMALLOC area in Linux-5.1-rc1 hence we get
below warning in Linux RISC-V 32bit kernel. This warning does not show-up
in Linux RISC-V 64bit kernel due to large VMALLOC area.

WARNING: CPU: 0 PID: 22 at mm/vmalloc.c:150 vmap_page_range_noflush+0x134/0x15c
Modules linked in:
CPU: 0 PID: 22 Comm: kworker/0:1 Not tainted 5.1.0-rc1-00005-gebc2f658040e #1
Workqueue: events pcpu_balance_workfn
Call Trace:
[<c002b950>] walk_stackframe+0x0/0xa0
[<c002baac>] show_stack+0x28/0x32
[<c0587354>] dump_stack+0x62/0x7e
[<c002fdee>] __warn+0x98/0xce
[<c002fe52>] warn_slowpath_null+0x2e/0x3c
[<c00e71ce>] vmap_page_range_noflush+0x134/0x15c
[<c00e7886>] map_kernel_range_noflush+0xc/0x14
[<c00d54b8>] pcpu_populate_chunk+0x19e/0x236
[<c00d610e>] pcpu_balance_workfn+0x448/0x464
[<c00408d6>] process_one_work+0x16c/0x2ea
[<c0040b46>] worker_thread+0xf2/0x3b2
[<c004519a>] kthread+0xce/0xdc
[<c002a974>] ret_from_exception+0x0/0xc

This patch fixes above warning by placing FIXMAP area below VMALLOC area.

Fixes: f2c17aabc9 ("RISC-V: Implement compile-time fixed mappings")
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-03-28 23:16:04 -07:00
..
asm-offsets.h
…
asm-prototypes.h
RISC-V: include linux/ftrace.h in asm-prototypes.h
2018-09-24 13:12:27 -07:00
asm.h
RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macros
2017-11-30 10:01:10 -08:00
atomic.h
riscv, atomic: Add #define's for the atomic_{cmp,}xchg_*() variants
2018-12-21 08:10:30 -08:00
barrier.h
riscv/barrier: Define __smp_{store_release,load_acquire}
2018-04-02 19:59:43 -07:00
bitops.h
RISC-V: __test_and_op_bit_ord should be strongly ordered
2017-11-28 14:04:05 -08:00
bug.h
RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macros
2017-11-30 10:01:10 -08:00
cache.h
…
cacheflush.h
riscv: use NULL instead of a plain 0
2018-06-07 08:01:50 -07:00
cmpxchg.h
riscv/atomic: Strengthen implementations with fences
2018-04-02 19:59:44 -07:00
csr.h
RISC-V: add a definition for the SIE SEIE bit
2018-08-13 08:31:31 -07:00
current.h
…
delay.h
…
elf.h
Move EM_RISCV into elf-em.h
2018-10-31 12:13:47 -07:00
fence.h
riscv/spinlock: Strengthen implementations with fences
2018-04-02 19:59:43 -07:00
fixmap.h
RISC-V: Fix FIXMAP_TOP to avoid overlap with VMALLOC area
2019-03-28 23:16:04 -07:00
ftrace.h
riscv/ftrace: Add DYNAMIC_FTRACE_WITH_REGS support
2018-04-02 19:59:13 -07:00
futex.h
Remove 'type' argument from access_ok() function
2019-01-03 18:57:57 -08:00
hwcap.h
…
io.h
riscv: io: Update __io_[p]ar() macros to take an argument
2019-02-28 17:23:12 +00:00
irq.h
RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h
2018-08-13 08:31:31 -07:00
irqflags.h
riscv: rename SR_* constants to match the spec
2018-01-07 15:14:39 -08:00
Kbuild
riscv: remove redundant kernel-space generic-y
2019-01-06 09:46:51 +09:00
kprobes.h
…
linkage.h
…
mmu_context.h
riscv: inline set_pgdir into its only caller
2018-01-30 19:16:17 -08:00
mmu.h
RISC-V: Flush I$ when making a dirty page executable
2017-11-30 12:58:25 -08:00
module.h
RISC-V: Support MODULE_SECTIONS mechanism on RV32
2019-01-07 08:19:20 -08:00
page.h
RISC-V: asm/page.h: fix spelling mistake "CONFIG_64BITS" -> "CONFIG_64BIT"
2019-01-23 12:56:20 -08:00
pci.h
PCI: remove PCI_DMA_BUS_IS_PHYS
2018-05-07 07:15:41 +02:00
perf_event.h
RISC-V: Fix !CONFIG_SMP compilation error
2018-08-13 08:31:32 -07:00
pgalloc.h
mm: treewide: remove unused address argument from pte_alloc functions
2019-01-04 13:13:47 -08:00
pgtable-32.h
…
pgtable-64.h
…
pgtable-bits.h
riscv: Add pte bit to distinguish swap from invalid
2019-02-11 15:24:45 -08:00
pgtable.h
RISC-V: Move setup_bootmem() to mm/init.c
2019-02-21 11:25:49 +05:30
processor.h
riscv: Adjust mmap base address at a third of task size
2019-01-25 10:50:53 -08:00
ptrace.h
riscv: add audit support
2019-01-07 08:22:39 -08:00
sbi.h
…
smp.h
RISC-V: Move cpuid to hartid mapping to SMP.
2019-03-04 10:40:38 -08:00
spinlock_types.h
…
spinlock.h
riscv/spinlock: Strengthen implementations with fences
2018-04-02 19:59:43 -07:00
string.h
…
switch_to.h
Auto-detect whether a FPU exists
2018-10-22 17:02:23 -07:00
syscall.h
riscv: add audit support
2019-01-07 08:22:39 -08:00
thread_info.h
riscv: add audit support
2019-01-07 08:22:39 -08:00
timex.h
RISC-V: Use define for get_cycles like other architectures
2017-11-30 10:12:21 -08:00
tlb.h
riscv: tlb: Provide definition of tlb_flush() before including tlb.h
2018-08-28 12:58:35 -07:00
tlbflush.h
RISC-V: Use Linux logical CPU number instead of hartid
2018-10-22 17:03:37 -07:00
uaccess.h
riscv: fix accessing 8-byte variable from RV32
2019-03-26 18:24:51 -07:00
unistd.h
riscv: define NR_syscalls in unistd.h
2019-01-07 08:22:41 -08:00
vdso.h
RISC-V: Define sys_riscv_flush_icache when SMP=n
2018-08-20 10:55:24 -07:00
word-at-a-time.h
…