fab957c11e
This contains all the code that directly interfaces with the RISC-V memory model. While this code corforms to the current RISC-V ISA specifications (user 2.2 and priv 1.10), the memory model is somewhat underspecified in those documents. There is a working group that hopes to produce a formal memory model by the end of the year, but my understanding is that the basic definitions we're relying on here won't change significantly. Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
40 lines
1.1 KiB
C
40 lines
1.1 KiB
C
/*
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* Copyright (C) 2015 Regents of the University of California
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _ASM_RISCV_CACHEFLUSH_H
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#define _ASM_RISCV_CACHEFLUSH_H
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#include <asm-generic/cacheflush.h>
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#undef flush_icache_range
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#undef flush_icache_user_range
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static inline void local_flush_icache_all(void)
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{
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asm volatile ("fence.i" ::: "memory");
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}
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#ifndef CONFIG_SMP
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#define flush_icache_range(start, end) local_flush_icache_all()
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#define flush_icache_user_range(vma, pg, addr, len) local_flush_icache_all()
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#else /* CONFIG_SMP */
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#define flush_icache_range(start, end) sbi_remote_fence_i(0)
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#define flush_icache_user_range(vma, pg, addr, len) sbi_remote_fence_i(0)
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#endif /* CONFIG_SMP */
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#endif /* _ASM_RISCV_CACHEFLUSH_H */
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