f75b99d5a7
When allocating space for 32-bit BARs, we previously limited RESOURCE
addresses so they would fit in 32 bits. However, the BUS address need not
be the same as the resource address, and it's the bus address that must fit
in the 32-bit BAR.
This patch adds:
- pci_clip_resource_to_region(), which clips a resource so it contains
only the range that maps to the specified bus address region, e.g., to
clip a resource to 32-bit bus addresses, and
- pci_bus_alloc_from_region(), which allocates space for a resource from
the specified bus address region,
and changes pci_bus_alloc_resource() to allocate space for 64-bit BARs from
the entire bus address region, and space for 32-bit BARs from only the bus
address region below 4GB.
If we had this window:
pci_root HWP0002:0a: host bridge window [mem 0xf0180000000-0xf01fedfffff] (bus address [0x80000000-0xfedfffff])
we previously could not put a 32-bit BAR there, because the CPU addresses
don't fit in 32 bits. This patch fixes this, so we can use this space for
32-bit BARs.
It's also possible (though unlikely) to have resources with 32-bit CPU
addresses but bus addresses above 4GB. In this case the previous code
would allocate space that a 32-bit BAR could not map.
Remove PCIBIOS_MAX_MEM_32, which is no longer used.
[bhelgaas: reworked starting from http://lkml.kernel.org/r/1386658484-15774-3-git-send-email-yinghai@kernel.org]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
162 lines
3.9 KiB
C
162 lines
3.9 KiB
C
#ifndef _ASM_X86_PCI_H
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#define _ASM_X86_PCI_H
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#include <linux/mm.h> /* for struct page */
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <asm/scatterlist.h>
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#include <asm/io.h>
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#include <asm/x86_init.h>
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#ifdef __KERNEL__
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struct pci_sysdata {
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int domain; /* PCI domain */
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int node; /* NUMA node */
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#ifdef CONFIG_ACPI
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struct acpi_device *companion; /* ACPI companion device */
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#endif
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#ifdef CONFIG_X86_64
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void *iommu; /* IOMMU private data */
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#endif
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};
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extern int pci_routeirq;
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extern int noioapicquirk;
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extern int noioapicreroute;
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/* scan a bus after allocating a pci_sysdata for it */
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extern struct pci_bus *pci_scan_bus_on_node(int busno, struct pci_ops *ops,
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int node);
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extern struct pci_bus *pci_scan_bus_with_sysdata(int busno);
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#ifdef CONFIG_PCI
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#ifdef CONFIG_PCI_DOMAINS
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static inline int pci_domain_nr(struct pci_bus *bus)
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{
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struct pci_sysdata *sd = bus->sysdata;
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return sd->domain;
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}
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static inline int pci_proc_domain(struct pci_bus *bus)
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{
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return pci_domain_nr(bus);
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}
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#endif
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/* Can be used to override the logic in pci_scan_bus for skipping
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already-configured bus numbers - to be used for buggy BIOSes
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or architectures with incomplete PCI setup by the loader */
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extern unsigned int pcibios_assign_all_busses(void);
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extern int pci_legacy_init(void);
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# ifdef CONFIG_ACPI
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# define x86_default_pci_init pci_acpi_init
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# else
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# define x86_default_pci_init pci_legacy_init
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# endif
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#else
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# define pcibios_assign_all_busses() 0
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# define x86_default_pci_init NULL
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#endif
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extern unsigned long pci_mem_start;
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#define PCIBIOS_MIN_IO 0x1000
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#define PCIBIOS_MIN_MEM (pci_mem_start)
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#define PCIBIOS_MIN_CARDBUS_IO 0x4000
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extern int pcibios_enabled;
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void pcibios_config_init(void);
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struct pci_bus *pcibios_scan_root(int bus);
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void pcibios_set_master(struct pci_dev *dev);
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void pcibios_penalize_isa_irq(int irq, int active);
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struct irq_routing_table *pcibios_get_irq_routing_table(void);
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int pcibios_set_irq_routing(struct pci_dev *dev, int pin, int irq);
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#define HAVE_PCI_MMAP
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extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state,
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int write_combine);
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#ifdef CONFIG_PCI
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extern void early_quirks(void);
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static inline void pci_dma_burst_advice(struct pci_dev *pdev,
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enum pci_dma_burst_strategy *strat,
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unsigned long *strategy_parameter)
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{
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*strat = PCI_DMA_BURST_INFINITY;
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*strategy_parameter = ~0UL;
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}
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#else
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static inline void early_quirks(void) { }
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#endif
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extern void pci_iommu_alloc(void);
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#ifdef CONFIG_PCI_MSI
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/* implemented in arch/x86/kernel/apic/io_apic. */
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struct msi_desc;
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int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
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void native_teardown_msi_irq(unsigned int irq);
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void native_restore_msi_irqs(struct pci_dev *dev, int irq);
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int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc,
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unsigned int irq_base, unsigned int irq_offset);
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#else
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#define native_setup_msi_irqs NULL
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#define native_teardown_msi_irq NULL
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#endif
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#define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys)
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#endif /* __KERNEL__ */
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#ifdef CONFIG_X86_64
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#include <asm/pci_64.h>
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#endif
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/* implement the pci_ DMA API in terms of the generic device dma_ one */
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#include <asm-generic/pci-dma-compat.h>
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/* generic pci stuff */
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#include <asm-generic/pci.h>
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#ifdef CONFIG_NUMA
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/* Returns the node based on pci bus */
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static inline int __pcibus_to_node(const struct pci_bus *bus)
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{
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const struct pci_sysdata *sd = bus->sysdata;
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return sd->node;
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}
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static inline const struct cpumask *
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cpumask_of_pcibus(const struct pci_bus *bus)
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{
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int node;
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node = __pcibus_to_node(bus);
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return (node == -1) ? cpu_online_mask :
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cpumask_of_node(node);
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}
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#endif
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struct pci_setup_rom {
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struct setup_data data;
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uint16_t vendor;
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uint16_t devid;
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uint64_t pcilen;
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unsigned long segment;
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unsigned long bus;
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unsigned long device;
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unsigned long function;
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uint8_t romdata[0];
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};
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#endif /* _ASM_X86_PCI_H */
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