xiaomi-sm8450/android_kernel_xiaomi_sm8450
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f6635f873a605576fa1983c605655a8721475c22
android_kernel_xiaomi_sm8450/arch/riscv/include/asm
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Gary Guo f6635f873a riscv: move switch_mm to its own file 
switch_mm is an expensive operations that has two users.
flush_icache_deferred is only called within switch_mm and can be moved
together. The function is expected to be more complicated when ASID
support is added, so clean up eagerly.

By moving them to a separate file we also removes some excessive
dependency of tlbflush.h and cacheflush.h.

Signed-off-by: Gary Guo <gary@garyguo.net>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-05-16 20:42:12 -07:00
..
asm-offsets.h
…
asm-prototypes.h
RISC-V: include linux/ftrace.h in asm-prototypes.h
2018-09-24 13:12:27 -07:00
asm.h
RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macros
2017-11-30 10:01:10 -08:00
atomic.h
riscv, atomic: Add #define's for the atomic_{cmp,}xchg_*() variants
2018-12-21 08:10:30 -08:00
barrier.h
riscv/barrier: Define __smp_{store_release,load_acquire}
2018-04-02 19:59:43 -07:00
bitops.h
RISC-V: __test_and_op_bit_ord should be strongly ordered
2017-11-28 14:04:05 -08:00
bug.h
RISC-V: use RISCV_{INT,SHORT} instead of {INT,SHORT} for asm macros
2017-11-30 10:01:10 -08:00
cache.h
…
cacheflush.h
riscv: move flush_icache_{all,mm} to cacheflush.c
2019-05-16 20:42:12 -07:00
cmpxchg.h
riscv/atomic: Strengthen implementations with fences
2018-04-02 19:59:44 -07:00
csr.h
RISC-V: Access CSRs using CSR numbers
2019-05-16 20:42:11 -07:00
current.h
…
delay.h
…
elf.h
riscv: remove unreachable big endian code
2019-04-25 14:51:10 -07:00
fence.h
riscv/spinlock: Strengthen implementations with fences
2018-04-02 19:59:43 -07:00
fixmap.h
RISC-V: Fix FIXMAP_TOP to avoid overlap with VMALLOC area
2019-03-28 23:16:04 -07:00
ftrace.h
riscv/ftrace: Add DYNAMIC_FTRACE_WITH_REGS support
2018-04-02 19:59:13 -07:00
futex.h
riscv: remove CONFIG_RISCV_ISA_A
2019-04-25 14:51:10 -07:00
hwcap.h
…
io.h
riscv: io: Update __io_[p]ar() macros to take an argument
2019-02-28 17:23:12 +00:00
irq.h
RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h
2018-08-13 08:31:31 -07:00
irqflags.h
RISC-V: Access CSRs using CSR numbers
2019-05-16 20:42:11 -07:00
Kbuild
riscv: use asm-generic/extable.h
2019-04-25 14:51:09 -07:00
kprobes.h
…
linkage.h
…
mmu_context.h
riscv: move switch_mm to its own file
2019-05-16 20:42:12 -07:00
mmu.h
RISC-V: Flush I$ when making a dirty page executable
2017-11-30 12:58:25 -08:00
module.h
RISC-V: Support MODULE_SECTIONS mechanism on RV32
2019-01-07 08:19:20 -08:00
page.h
RISC-V: asm/page.h: fix spelling mistake "CONFIG_64BITS" -> "CONFIG_64BIT"
2019-01-23 12:56:20 -08:00
pci.h
PCI: remove PCI_DMA_BUS_IS_PHYS
2018-05-07 07:15:41 +02:00
perf_event.h
RISC-V: Fix !CONFIG_SMP compilation error
2018-08-13 08:31:32 -07:00
pgalloc.h
mm: treewide: remove unused address argument from pte_alloc functions
2019-01-04 13:13:47 -08:00
pgtable-32.h
…
pgtable-64.h
…
pgtable-bits.h
riscv: Add pte bit to distinguish swap from invalid
2019-02-11 15:24:45 -08:00
pgtable.h
RISC-V: Move setup_bootmem() to mm/init.c
2019-02-21 11:25:49 +05:30
processor.h
riscv: Adjust mmap base address at a third of task size
2019-01-25 10:50:53 -08:00
ptrace.h
riscv: remove duplicate macros from ptrace.h
2019-04-25 14:51:11 -07:00
sbi.h
…
smp.h
RISC-V: Move cpuid to hartid mapping to SMP.
2019-03-04 10:40:38 -08:00
spinlock_types.h
…
spinlock.h
riscv/spinlock: Strengthen implementations with fences
2018-04-02 19:59:43 -07:00
string.h
…
switch_to.h
Auto-detect whether a FPU exists
2018-10-22 17:02:23 -07:00
syscall.h
syscalls: Remove start and number from syscall_set_arguments() args
2019-04-05 09:27:23 -04:00
thread_info.h
riscv: turn mm_segment_t into a struct
2019-04-25 14:51:10 -07:00
timex.h
RISC-V: Use define for get_cycles like other architectures
2017-11-30 10:12:21 -08:00
tlb.h
riscv: tlb: Provide definition of tlb_flush() before including tlb.h
2018-08-28 12:58:35 -07:00
tlbflush.h
RISC-V: Use Linux logical CPU number instead of hartid
2018-10-22 17:03:37 -07:00
uaccess.h
riscv: remove unreachable big endian code
2019-04-25 14:51:10 -07:00
unistd.h
riscv: define NR_syscalls in unistd.h
2019-01-07 08:22:41 -08:00
vdso.h
RISC-V: Define sys_riscv_flush_icache when SMP=n
2018-08-20 10:55:24 -07:00
word-at-a-time.h
…