Atish Patra f1e58583b9 RISC-V: Support cpu hotplug ...

This patch enable support for cpu hotplug in RISC-V. It uses SBI HSM
extension to online/offline any hart. As a result, the harts are
returned to firmware once they are offline. If the harts are brought
online afterwards, they re-enter Linux kernel as if a secondary hart
booted for the first time. All booting requirements are honored during
this process.

Tested both on QEMU and HighFive Unleashed board with. Test result follows.

---------------------------------------------------
Offline cpu 2
---------------------------------------------------
$ echo 0 > /sys/devices/system/cpu/cpu2/online
[   32.828684] CPU2: off
$ cat /proc/cpuinfo
processor       : 0
hart            : 0
isa             : rv64imafdcsu
mmu             : sv48

processor       : 1
hart            : 1
isa             : rv64imafdcsu
mmu             : sv48

processor       : 3
hart            : 3
isa             : rv64imafdcsu
mmu             : sv48

processor       : 4
hart            : 4
isa             : rv64imafdcsu
mmu             : sv48

processor       : 5
hart            : 5
isa             : rv64imafdcsu
mmu             : sv48

processor       : 6
hart            : 6
isa             : rv64imafdcsu
mmu             : sv48

processor       : 7
hart            : 7
isa             : rv64imafdcsu
mmu             : sv48

---------------------------------------------------
online cpu 2
---------------------------------------------------
$ echo 1 > /sys/devices/system/cpu/cpu2/online
$ cat /proc/cpuinfo
processor       : 0
hart            : 0
isa             : rv64imafdcsu
mmu             : sv48

processor       : 1
hart            : 1
isa             : rv64imafdcsu
mmu             : sv48

processor       : 2
hart            : 2
isa             : rv64imafdcsu
mmu             : sv48

processor       : 3
hart            : 3
isa             : rv64imafdcsu
mmu             : sv48

processor       : 4
hart            : 4
isa             : rv64imafdcsu
mmu             : sv48

processor       : 5
hart            : 5
isa             : rv64imafdcsu
mmu             : sv48

processor       : 6
hart            : 6
isa             : rv64imafdcsu
mmu             : sv48

processor       : 7
hart            : 7
isa             : rv64imafdcsu
mmu             : sv48

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>

2020-03-31 11:28:30 -07:00

..

vdso

riscv: delete temporary files

2020-01-18 13:22:13 -08:00

.gitignore

RISC-V: Build Infrastructure

2017-09-26 15:26:49 -07:00

asm-offsets.c

riscv: abstract out CSR names for supervisor vs machine mode

2019-11-05 09:20:42 -08:00

cacheinfo.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286

2019-06-05 17:36:37 +02:00

clint.c

riscv: provide native clint access for M-mode

2019-11-17 15:17:39 -08:00

cpu_ops_sbi.c

RISC-V: Support cpu hotplug

2020-03-31 11:28:30 -07:00

cpu_ops_spinwait.c

RISC-V: Add cpu_ops and modify default booting method

2020-03-31 11:25:56 -07:00

cpu_ops.c

RISC-V: Add supported for ordered booting method using HSM

2020-03-31 11:27:50 -07:00

cpu-hotplug.c

RISC-V: Support cpu hotplug

2020-03-31 11:28:30 -07:00

cpu.c

RISC-V: Remove unsupported isa string info print

2019-10-28 11:13:59 -07:00

cpufeature.c

riscv: add missing header file includes

2019-10-28 00:46:01 -07:00

entry.S

RISC-V: Inline the assembly register save/restore macros

2020-03-03 10:33:21 -08:00

fpu.S

riscv: abstract out CSR names for supervisor vs machine mode

2019-11-05 09:20:42 -08:00

ftrace.c

riscv: patch code by fixmap mapping

2020-03-26 09:24:55 -07:00

head.h

riscv: add prototypes for assembly language functions from head.S

2019-10-28 00:46:00 -07:00

head.S

RISC-V: Add supported for ordered booting method using HSM

2020-03-31 11:27:50 -07:00

irq.c

riscv: prefix IRQ_ macro names with an RV_ namespace

2020-01-04 21:48:59 -08:00

Makefile

RISC-V: Support cpu hotplug

2020-03-31 11:28:30 -07:00

mcount-dyn.S

riscv/ftrace: Add DYNAMIC_FTRACE_WITH_REGS support

2018-04-02 19:59:13 -07:00

mcount.S

RISC-V: remove the unused return_to_handler export

2018-10-22 17:38:12 -07:00

module-sections.c

riscv: add missing header file includes

2019-10-28 00:46:01 -07:00

module.c

riscv: Use pr_warn instead of pr_warning

2019-10-18 10:48:36 +02:00

module.lds

RISC-V: Add section of GOT.PLT for kernel module

2018-04-02 20:00:54 -07:00

patch.c

riscv: introduce interfaces to patch kernel code

2020-03-26 09:24:52 -07:00

perf_callchain.c

riscv: abstract out CSR names for supervisor vs machine mode

2019-11-05 09:20:42 -08:00

perf_event.c

RISC-V: Access CSRs using CSR numbers

2019-05-16 20:42:11 -07:00

perf_regs.c

riscv: Add support for perf registers sampling

2019-09-05 00:48:58 -07:00

process.c

RISC-V: Stop relying on GCC's register allocator's hueristics

2020-03-03 10:28:13 -08:00

ptrace.c

Merge tag 'seccomp-v5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux

2019-11-30 17:23:16 -08:00

reset.c

riscv: cleanup the default power off implementation

2019-11-13 13:22:52 -08:00

riscv_ksyms.c

riscv: Add KASAN support

2020-01-22 13:09:58 -08:00

sbi.c

RISC-V: Export SBI error to linux error mapping function

2020-03-31 11:26:00 -07:00

setup.c

RISC-V: Support cpu hotplug

2020-03-31 11:28:30 -07:00

signal.c

riscv: add nommu support

2019-11-17 15:17:39 -08:00

smp.c

riscv: provide native clint access for M-mode

2019-11-17 15:17:39 -08:00

smpboot.c

RISC-V: Add supported for ordered booting method using HSM

2020-03-31 11:27:50 -07:00

stacktrace.c

RISC-V: Stop relying on GCC's register allocator's hueristics

2020-03-03 10:28:13 -08:00

sys_riscv.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286

2019-06-05 17:36:37 +02:00

syscall_table.c

riscv: add missing header file includes

2019-10-28 00:46:01 -07:00

time.c

riscv: add missing header file includes

2019-10-28 00:46:01 -07:00

traps.c

RISC-V: Add supported for ordered booting method using HSM

2020-03-31 11:27:50 -07:00

vdso.c

riscv: add missing header file includes

2019-10-28 00:46:01 -07:00

vmlinux.lds.S

RISC-V: Move relocate and few other functions out of __init

2020-03-31 11:25:50 -07:00