0d00449c7a
A few exceptions (like #DB and #BP) can happen at any location in the code, this then means that tracers should treat events from these exceptions as NMI-like. The interrupted context could be holding locks with interrupts disabled for instance. Similarly, #MC is an actual NMI-like exception. All of them use ist_enter() which only concerns itself with RCU, but does not do any of the other setup that NMIs need. This means things like: printk() raw_spin_lock_irq(&logbuf_lock); <#DB/#BP/#MC> printk() raw_spin_lock_irq(&logbuf_lock); are entirely possible (well, not really since printk tries hard to play nice, but the concept stands). So replace ist_enter() with nmi_enter(). Also observe that any nmi_enter() caller must be both notrace and NOKPROBE, or in the noinstr text section. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexandre Chartre <alexandre.chartre@oracle.com> Link: https://lkml.kernel.org/r/20200505134101.525508608@linutronix.de
73 lines
1.8 KiB
C
73 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* P5 specific Machine Check Exception Reporting
|
|
* (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk>
|
|
*/
|
|
#include <linux/interrupt.h>
|
|
#include <linux/kernel.h>
|
|
#include <linux/types.h>
|
|
#include <linux/smp.h>
|
|
#include <linux/hardirq.h>
|
|
|
|
#include <asm/processor.h>
|
|
#include <asm/traps.h>
|
|
#include <asm/tlbflush.h>
|
|
#include <asm/mce.h>
|
|
#include <asm/msr.h>
|
|
|
|
#include "internal.h"
|
|
|
|
/* By default disabled */
|
|
int mce_p5_enabled __read_mostly;
|
|
|
|
/* Machine check handler for Pentium class Intel CPUs: */
|
|
static void pentium_machine_check(struct pt_regs *regs, long error_code)
|
|
{
|
|
u32 loaddr, hi, lotype;
|
|
|
|
nmi_enter();
|
|
|
|
rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
|
|
rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
|
|
|
|
pr_emerg("CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n",
|
|
smp_processor_id(), loaddr, lotype);
|
|
|
|
if (lotype & (1<<5)) {
|
|
pr_emerg("CPU#%d: Possible thermal failure (CPU on fire ?).\n",
|
|
smp_processor_id());
|
|
}
|
|
|
|
add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
|
|
|
|
nmi_exit();
|
|
}
|
|
|
|
/* Set up machine check reporting for processors with Intel style MCE: */
|
|
void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
|
|
{
|
|
u32 l, h;
|
|
|
|
/* Default P5 to off as its often misconnected: */
|
|
if (!mce_p5_enabled)
|
|
return;
|
|
|
|
/* Check for MCE support: */
|
|
if (!cpu_has(c, X86_FEATURE_MCE))
|
|
return;
|
|
|
|
machine_check_vector = pentium_machine_check;
|
|
/* Make sure the vector pointer is visible before we enable MCEs: */
|
|
wmb();
|
|
|
|
/* Read registers before enabling: */
|
|
rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
|
|
rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
|
|
pr_info("Intel old style machine check architecture supported.\n");
|
|
|
|
/* Enable MCE: */
|
|
cr4_set_bits(X86_CR4_MCE);
|
|
pr_info("Intel old style machine check reporting enabled on CPU#%d.\n",
|
|
smp_processor_id());
|
|
}
|