e2c9e67e44
The Allwinner H6 SPI controller has advanced features over the H3 version, but remains compatible with it. Document the usual "specific", "fallback" compatible string pair. Also add the R40 version while at it. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
113 lines
2.1 KiB
YAML
113 lines
2.1 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/allwinner,sun6i-a31-spi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner A31 SPI Controller Device Tree Bindings
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allOf:
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- $ref: "spi-controller.yaml"
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>
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- Maxime Ripard <mripard@kernel.org>
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properties:
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"#address-cells": true
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"#size-cells": true
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compatible:
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oneOf:
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- const: allwinner,sun6i-a31-spi
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- const: allwinner,sun8i-h3-spi
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- items:
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- enum:
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- allwinner,sun8i-r40-spi
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- allwinner,sun50i-h6-spi
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- const: allwinner,sun8i-h3-spi
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: Bus Clock
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- description: Module Clock
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clock-names:
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items:
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- const: ahb
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- const: mod
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resets:
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maxItems: 1
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dmas:
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items:
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- description: RX DMA Channel
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- description: TX DMA Channel
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dma-names:
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items:
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- const: rx
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- const: tx
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num-cs: true
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patternProperties:
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"^.*@[0-9a-f]+":
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type: object
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properties:
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reg:
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items:
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minimum: 0
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maximum: 4
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spi-rx-bus-width:
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const: 1
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spi-tx-bus-width:
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const: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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spi1: spi@1c69000 {
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compatible = "allwinner,sun6i-a31-spi";
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reg = <0x01c69000 0x1000>;
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interrupts = <0 66 4>;
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clocks = <&ahb1_gates 21>, <&spi1_clk>;
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clock-names = "ahb", "mod";
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resets = <&ahb1_rst 21>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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- |
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spi0: spi@1c68000 {
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compatible = "allwinner,sun8i-h3-spi";
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reg = <0x01c68000 0x1000>;
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interrupts = <0 65 4>;
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clocks = <&ccu 30>, <&ccu 82>;
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clock-names = "ahb", "mod";
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dmas = <&dma 23>, <&dma 23>;
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dma-names = "rx", "tx";
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resets = <&ccu 15>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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...
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