ee4a5f838c
This patch adds suspend function for i.MX6UL, it supports "standby" and "mem" mode, for "standby" mode, SoC will enter STOP mode only, while for "mem" mode, SoC will enter STOP mode and DDR IO will be set to low power mode. As i.MX6UL contains a "Cortex-A7" ARM core which has no PL310, so we need to avoid any PL310 operations during suspend/resume, also, we need to flush Cortex-A7's inernal L2 cache before suspend. Signed-off-by: Anson Huang <b20788@freescale.com>
91 lines
2.1 KiB
C
91 lines
2.1 KiB
C
/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/irqchip.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
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#include <linux/micrel_phy.h>
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#include <linux/of_platform.h>
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#include <linux/phy.h>
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#include <linux/regmap.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include "common.h"
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static void __init imx6ul_enet_clk_init(void)
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{
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struct regmap *gpr;
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gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
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if (!IS_ERR(gpr))
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regmap_update_bits(gpr, IOMUXC_GPR1, IMX6UL_GPR1_ENET_CLK_DIR,
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IMX6UL_GPR1_ENET_CLK_OUTPUT);
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else
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pr_err("failed to find fsl,imx6ul-iomux-gpr regmap\n");
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}
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static int ksz8081_phy_fixup(struct phy_device *dev)
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{
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if (dev && dev->interface == PHY_INTERFACE_MODE_MII) {
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phy_write(dev, 0x1f, 0x8110);
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phy_write(dev, 0x16, 0x201);
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} else if (dev && dev->interface == PHY_INTERFACE_MODE_RMII) {
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phy_write(dev, 0x1f, 0x8190);
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phy_write(dev, 0x16, 0x202);
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}
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return 0;
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}
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static void __init imx6ul_enet_phy_init(void)
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{
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if (IS_BUILTIN(CONFIG_PHYLIB))
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phy_register_fixup_for_uid(PHY_ID_KSZ8081, 0xffffffff,
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ksz8081_phy_fixup);
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}
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static inline void imx6ul_enet_init(void)
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{
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imx6ul_enet_clk_init();
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imx6ul_enet_phy_init();
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}
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static void __init imx6ul_init_machine(void)
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{
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struct device *parent;
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parent = imx_soc_device_init();
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if (parent == NULL)
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pr_warn("failed to initialize soc device\n");
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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imx6ul_enet_init();
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imx_anatop_init();
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imx6ul_pm_init();
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}
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static void __init imx6ul_init_irq(void)
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{
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imx_init_revision_from_anatop();
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imx_src_init();
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irqchip_init();
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imx6_pm_ccm_init("fsl,imx6ul-ccm");
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}
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static const char *imx6ul_dt_compat[] __initconst = {
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"fsl,imx6ul",
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NULL,
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};
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DT_MACHINE_START(IMX6UL, "Freescale i.MX6 Ultralite (Device Tree)")
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.init_irq = imx6ul_init_irq,
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.init_machine = imx6ul_init_machine,
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.dt_compat = imx6ul_dt_compat,
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MACHINE_END
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