Yonghong Song ed8dfc46e0 MIPS: Netlogic: L1D cacheflush before thread enable on XLPII ...

On XLPII CPUs, the L1D cache has to be flushed with regular cache
operations before enabling threads in a core.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6276/

2014-01-24 22:39:47 +01:00

..

earlycons.c

MIPS: Netlogic: early console fix

2012-07-24 18:24:44 +02:00

irq.c

MIPS: Netlogic: Add MSI support for XLP

2014-01-24 22:39:46 +01:00

Makefile

MIPS: Netlogic: Initialization when !CONFIG_SMP

2013-06-13 17:46:42 +02:00

nlm-dma.c

MIPS: Netlogic: SWIOTLB dma ops for 32-bit DMA

2013-06-13 17:46:40 +02:00

reset.S

MIPS: Netlogic: L1D cacheflush before thread enable on XLPII

2014-01-24 22:39:47 +01:00

smp.c

MIPS: Panic messages should not end in \n.

2013-10-29 21:24:19 +01:00

smpboot.S

MIPS: Netlogic: Some cleanups for assembly code

2014-01-24 22:39:47 +01:00

time.c

MIPS: Netlogic: XLP2XX CPU and PIC frequency

2013-09-03 23:22:19 +02:00