e6046b5e69
For a long time the mt7621 uses a fixed cpu clock which causes a problem if the cpu frequency is not 880MHz. This patch fixes the cpu clock calculation and adds the cpu/bus clkdev which will be used in dts. Ported from OpenWrt: c7ca224299 ramips: fix cpu clock of mt7621 and add dt clk devices Signed-off-by: Weijie Gao <hackpascal@gmail.com> Signed-off-by: Chuanhong Guo <gch981213@gmail.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: John Crispin <john@phrozen.org> Cc: linux-kernel@vger.kernel.org
59 lines
1.5 KiB
C
59 lines
1.5 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* Copyright (C) 2015 John Crispin <john@phrozen.org>
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*/
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#ifndef _MT7621_REGS_H_
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#define _MT7621_REGS_H_
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#define MT7621_PALMBUS_BASE 0x1C000000
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#define MT7621_PALMBUS_SIZE 0x03FFFFFF
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#define MT7621_SYSC_BASE 0x1E000000
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#define SYSC_REG_CHIP_NAME0 0x00
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#define SYSC_REG_CHIP_NAME1 0x04
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#define SYSC_REG_CHIP_REV 0x0c
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#define SYSC_REG_SYSTEM_CONFIG0 0x10
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#define SYSC_REG_SYSTEM_CONFIG1 0x14
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#define SYSC_REG_CLKCFG0 0x2c
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#define SYSC_REG_CUR_CLK_STS 0x44
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#define MEMC_REG_CPU_PLL 0x648
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#define CHIP_REV_PKG_MASK 0x1
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#define CHIP_REV_PKG_SHIFT 16
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#define CHIP_REV_VER_MASK 0xf
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#define CHIP_REV_VER_SHIFT 8
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#define CHIP_REV_ECO_MASK 0xf
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#define XTAL_MODE_SEL_MASK 0x7
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#define XTAL_MODE_SEL_SHIFT 6
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#define CPU_CLK_SEL_MASK 0x3
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#define CPU_CLK_SEL_SHIFT 30
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#define CUR_CPU_FDIV_MASK 0x1f
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#define CUR_CPU_FDIV_SHIFT 8
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#define CUR_CPU_FFRAC_MASK 0x1f
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#define CUR_CPU_FFRAC_SHIFT 0
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#define CPU_PLL_PREDIV_MASK 0x3
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#define CPU_PLL_PREDIV_SHIFT 12
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#define CPU_PLL_FBDIV_MASK 0x7f
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#define CPU_PLL_FBDIV_SHIFT 4
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#define MT7621_DRAM_BASE 0x0
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#define MT7621_DDR2_SIZE_MIN 32
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#define MT7621_DDR2_SIZE_MAX 256
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#define MT7621_CHIP_NAME0 0x3637544D
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#define MT7621_CHIP_NAME1 0x20203132
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#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
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#endif
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