e3b3d0f549
It's good to have SPDX identifiers in all files to make it easier to audit the kernel tree for correct licenses. Update the drivers/tty files files with the correct SPDX license identifier based on the license text in the file itself. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This work is based on a script and data from Thomas Gleixner, Philippe Ombredanne, and Kate Stewart. Cc: Jiri Slaby <jslaby@suse.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Chris Metcalf <cmetcalf@mellanox.com> Cc: Jiri Kosina <jikos@kernel.org> Cc: David Sterba <dsterba@suse.com> Cc: James Hogan <jhogan@kernel.org> Cc: Rob Herring <robh@kernel.org> Cc: Eric Anholt <eric@anholt.net> Cc: Stefan Wahren <stefan.wahren@i2se.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Ray Jui <rjui@broadcom.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: bcm-kernel-feedback-list@broadcom.com Cc: "James E.J. Bottomley" <jejb@parisc-linux.org> Cc: Helge Deller <deller@gmx.de> Cc: Joachim Eastwood <manabian@gmail.com> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Tobias Klauser <tklauser@distanz.ch> Cc: Russell King <linux@armlinux.org.uk> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Richard Genoud <richard.genoud@gmail.com> Cc: Alexander Shiyan <shc_work@mail.ru> Cc: Baruch Siach <baruch@tkos.co.il> Cc: "Maciej W. Rozycki" <macro@linux-mips.org> Cc: "Uwe Kleine-König" <kernel@pengutronix.de> Cc: Pat Gefre <pfg@sgi.com> Cc: "Guilherme G. Piccoli" <gpiccoli@linux.vnet.ibm.com> Cc: Jason Wessel <jason.wessel@windriver.com> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Sylvain Lemieux <slemieux.tyco@gmail.com> Cc: Carlo Caione <carlo@caione.org> Cc: Kevin Hilman <khilman@baylibre.com> Cc: Liviu Dudau <liviu.dudau@arm.com> Cc: Sudeep Holla <sudeep.holla@arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Andy Gross <andy.gross@linaro.org> Cc: David Brown <david.brown@linaro.org> Cc: "Andreas Färber" <afaerber@suse.de> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Laxman Dewangan <ldewangan@nvidia.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Barry Song <baohua@kernel.org> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Alexandre Torgue <alexandre.torgue@st.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Peter Korsgaard <jacmet@sunsite.dk> Cc: Timur Tabi <timur@tabi.org> Cc: Tony Prisk <linux@prisktech.co.nz> Cc: Michal Simek <michal.simek@xilinx.com> Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Kate Stewart <kstewart@linuxfoundation.org> Cc: Philippe Ombredanne <pombredanne@nexb.com> Cc: Jiri Slaby <jslaby@suse.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
171 lines
7.8 KiB
C
171 lines
7.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* include/linux/atmel_serial.h
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*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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*
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* USART registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef ATMEL_SERIAL_H
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#define ATMEL_SERIAL_H
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#define ATMEL_US_CR 0x00 /* Control Register */
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#define ATMEL_US_RSTRX BIT(2) /* Reset Receiver */
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#define ATMEL_US_RSTTX BIT(3) /* Reset Transmitter */
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#define ATMEL_US_RXEN BIT(4) /* Receiver Enable */
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#define ATMEL_US_RXDIS BIT(5) /* Receiver Disable */
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#define ATMEL_US_TXEN BIT(6) /* Transmitter Enable */
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#define ATMEL_US_TXDIS BIT(7) /* Transmitter Disable */
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#define ATMEL_US_RSTSTA BIT(8) /* Reset Status Bits */
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#define ATMEL_US_STTBRK BIT(9) /* Start Break */
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#define ATMEL_US_STPBRK BIT(10) /* Stop Break */
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#define ATMEL_US_STTTO BIT(11) /* Start Time-out */
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#define ATMEL_US_SENDA BIT(12) /* Send Address */
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#define ATMEL_US_RSTIT BIT(13) /* Reset Iterations */
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#define ATMEL_US_RSTNACK BIT(14) /* Reset Non Acknowledge */
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#define ATMEL_US_RETTO BIT(15) /* Rearm Time-out */
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#define ATMEL_US_DTREN BIT(16) /* Data Terminal Ready Enable */
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#define ATMEL_US_DTRDIS BIT(17) /* Data Terminal Ready Disable */
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#define ATMEL_US_RTSEN BIT(18) /* Request To Send Enable */
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#define ATMEL_US_RTSDIS BIT(19) /* Request To Send Disable */
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#define ATMEL_US_TXFCLR BIT(24) /* Transmit FIFO Clear */
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#define ATMEL_US_RXFCLR BIT(25) /* Receive FIFO Clear */
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#define ATMEL_US_TXFLCLR BIT(26) /* Transmit FIFO Lock Clear */
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#define ATMEL_US_FIFOEN BIT(30) /* FIFO enable */
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#define ATMEL_US_FIFODIS BIT(31) /* FIFO disable */
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#define ATMEL_US_MR 0x04 /* Mode Register */
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#define ATMEL_US_USMODE GENMASK(3, 0) /* Mode of the USART */
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#define ATMEL_US_USMODE_NORMAL 0
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#define ATMEL_US_USMODE_RS485 1
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#define ATMEL_US_USMODE_HWHS 2
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#define ATMEL_US_USMODE_MODEM 3
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#define ATMEL_US_USMODE_ISO7816_T0 4
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#define ATMEL_US_USMODE_ISO7816_T1 6
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#define ATMEL_US_USMODE_IRDA 8
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#define ATMEL_US_USCLKS GENMASK(5, 4) /* Clock Selection */
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#define ATMEL_US_USCLKS_MCK (0 << 4)
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#define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4)
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#define ATMEL_US_USCLKS_SCK (3 << 4)
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#define ATMEL_US_CHRL GENMASK(7, 6) /* Character Length */
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#define ATMEL_US_CHRL_5 (0 << 6)
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#define ATMEL_US_CHRL_6 (1 << 6)
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#define ATMEL_US_CHRL_7 (2 << 6)
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#define ATMEL_US_CHRL_8 (3 << 6)
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#define ATMEL_US_SYNC BIT(8) /* Synchronous Mode Select */
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#define ATMEL_US_PAR GENMASK(11, 9) /* Parity Type */
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#define ATMEL_US_PAR_EVEN (0 << 9)
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#define ATMEL_US_PAR_ODD (1 << 9)
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#define ATMEL_US_PAR_SPACE (2 << 9)
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#define ATMEL_US_PAR_MARK (3 << 9)
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#define ATMEL_US_PAR_NONE (4 << 9)
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#define ATMEL_US_PAR_MULTI_DROP (6 << 9)
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#define ATMEL_US_NBSTOP GENMASK(13, 12) /* Number of Stop Bits */
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#define ATMEL_US_NBSTOP_1 (0 << 12)
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#define ATMEL_US_NBSTOP_1_5 (1 << 12)
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#define ATMEL_US_NBSTOP_2 (2 << 12)
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#define ATMEL_US_CHMODE GENMASK(15, 14) /* Channel Mode */
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#define ATMEL_US_CHMODE_NORMAL (0 << 14)
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#define ATMEL_US_CHMODE_ECHO (1 << 14)
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#define ATMEL_US_CHMODE_LOC_LOOP (2 << 14)
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#define ATMEL_US_CHMODE_REM_LOOP (3 << 14)
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#define ATMEL_US_MSBF BIT(16) /* Bit Order */
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#define ATMEL_US_MODE9 BIT(17) /* 9-bit Character Length */
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#define ATMEL_US_CLKO BIT(18) /* Clock Output Select */
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#define ATMEL_US_OVER BIT(19) /* Oversampling Mode */
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#define ATMEL_US_INACK BIT(20) /* Inhibit Non Acknowledge */
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#define ATMEL_US_DSNACK BIT(21) /* Disable Successive NACK */
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#define ATMEL_US_MAX_ITER GENMASK(26, 24) /* Max Iterations */
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#define ATMEL_US_FILTER BIT(28) /* Infrared Receive Line Filter */
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#define ATMEL_US_IER 0x08 /* Interrupt Enable Register */
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#define ATMEL_US_RXRDY BIT(0) /* Receiver Ready */
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#define ATMEL_US_TXRDY BIT(1) /* Transmitter Ready */
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#define ATMEL_US_RXBRK BIT(2) /* Break Received / End of Break */
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#define ATMEL_US_ENDRX BIT(3) /* End of Receiver Transfer */
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#define ATMEL_US_ENDTX BIT(4) /* End of Transmitter Transfer */
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#define ATMEL_US_OVRE BIT(5) /* Overrun Error */
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#define ATMEL_US_FRAME BIT(6) /* Framing Error */
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#define ATMEL_US_PARE BIT(7) /* Parity Error */
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#define ATMEL_US_TIMEOUT BIT(8) /* Receiver Time-out */
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#define ATMEL_US_TXEMPTY BIT(9) /* Transmitter Empty */
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#define ATMEL_US_ITERATION BIT(10) /* Max number of Repetitions Reached */
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#define ATMEL_US_TXBUFE BIT(11) /* Transmission Buffer Empty */
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#define ATMEL_US_RXBUFF BIT(12) /* Reception Buffer Full */
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#define ATMEL_US_NACK BIT(13) /* Non Acknowledge */
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#define ATMEL_US_RIIC BIT(16) /* Ring Indicator Input Change */
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#define ATMEL_US_DSRIC BIT(17) /* Data Set Ready Input Change */
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#define ATMEL_US_DCDIC BIT(18) /* Data Carrier Detect Input Change */
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#define ATMEL_US_CTSIC BIT(19) /* Clear to Send Input Change */
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#define ATMEL_US_RI BIT(20) /* RI */
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#define ATMEL_US_DSR BIT(21) /* DSR */
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#define ATMEL_US_DCD BIT(22) /* DCD */
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#define ATMEL_US_CTS BIT(23) /* CTS */
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#define ATMEL_US_IDR 0x0c /* Interrupt Disable Register */
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#define ATMEL_US_IMR 0x10 /* Interrupt Mask Register */
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#define ATMEL_US_CSR 0x14 /* Channel Status Register */
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#define ATMEL_US_RHR 0x18 /* Receiver Holding Register */
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#define ATMEL_US_THR 0x1c /* Transmitter Holding Register */
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#define ATMEL_US_SYNH BIT(15) /* Transmit/Receive Sync */
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#define ATMEL_US_BRGR 0x20 /* Baud Rate Generator Register */
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#define ATMEL_US_CD GENMASK(15, 0) /* Clock Divider */
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#define ATMEL_US_FP_OFFSET 16 /* Fractional Part */
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#define ATMEL_US_FP_MASK 0x7
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#define ATMEL_US_RTOR 0x24 /* Receiver Time-out Register for USART */
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#define ATMEL_UA_RTOR 0x28 /* Receiver Time-out Register for UART */
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#define ATMEL_US_TO GENMASK(15, 0) /* Time-out Value */
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#define ATMEL_US_TTGR 0x28 /* Transmitter Timeguard Register */
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#define ATMEL_US_TG GENMASK(7, 0) /* Timeguard Value */
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#define ATMEL_US_FIDI 0x40 /* FI DI Ratio Register */
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#define ATMEL_US_NER 0x44 /* Number of Errors Register */
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#define ATMEL_US_IF 0x4c /* IrDA Filter Register */
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#define ATMEL_US_CMPR 0x90 /* Comparaison Register */
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#define ATMEL_US_FMR 0xa0 /* FIFO Mode Register */
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#define ATMEL_US_TXRDYM(data) (((data) & 0x3) << 0) /* TX Ready Mode */
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#define ATMEL_US_RXRDYM(data) (((data) & 0x3) << 4) /* RX Ready Mode */
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#define ATMEL_US_ONE_DATA 0x0
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#define ATMEL_US_TWO_DATA 0x1
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#define ATMEL_US_FOUR_DATA 0x2
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#define ATMEL_US_FRTSC BIT(7) /* FIFO RTS pin Control */
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#define ATMEL_US_TXFTHRES(thr) (((thr) & 0x3f) << 8) /* TX FIFO Threshold */
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#define ATMEL_US_RXFTHRES(thr) (((thr) & 0x3f) << 16) /* RX FIFO Threshold */
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#define ATMEL_US_RXFTHRES2(thr) (((thr) & 0x3f) << 24) /* RX FIFO Threshold2 */
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#define ATMEL_US_FLR 0xa4 /* FIFO Level Register */
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#define ATMEL_US_TXFL(reg) (((reg) >> 0) & 0x3f) /* TX FIFO Level */
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#define ATMEL_US_RXFL(reg) (((reg) >> 16) & 0x3f) /* RX FIFO Level */
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#define ATMEL_US_FIER 0xa8 /* FIFO Interrupt Enable Register */
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#define ATMEL_US_FIDR 0xac /* FIFO Interrupt Disable Register */
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#define ATMEL_US_FIMR 0xb0 /* FIFO Interrupt Mask Register */
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#define ATMEL_US_FESR 0xb4 /* FIFO Event Status Register */
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#define ATMEL_US_TXFEF BIT(0) /* Transmit FIFO Empty Flag */
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#define ATMEL_US_TXFFF BIT(1) /* Transmit FIFO Full Flag */
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#define ATMEL_US_TXFTHF BIT(2) /* Transmit FIFO Threshold Flag */
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#define ATMEL_US_RXFEF BIT(3) /* Receive FIFO Empty Flag */
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#define ATMEL_US_RXFFF BIT(4) /* Receive FIFO Full Flag */
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#define ATMEL_US_RXFTHF BIT(5) /* Receive FIFO Threshold Flag */
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#define ATMEL_US_TXFPTEF BIT(6) /* Transmit FIFO Pointer Error Flag */
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#define ATMEL_US_RXFPTEF BIT(7) /* Receive FIFO Pointer Error Flag */
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#define ATMEL_US_TXFLOCK BIT(8) /* Transmit FIFO Lock (FESR only) */
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#define ATMEL_US_RXFTHF2 BIT(9) /* Receive FIFO Threshold Flag 2 */
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#define ATMEL_US_NAME 0xf0 /* Ip Name */
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#define ATMEL_US_VERSION 0xfc /* Ip Version */
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#endif
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