15a9844458
Pull irq fixes from Thomas Gleixner:
"A set of fixes for interrupt chip drivers:
- Fix the fallout of the IPI as interrupt conversion in Kconfig and
the BCM2836 interrupt chip driver
- Fixes for interrupt affinity setting and the handling of
hierarchical irq domains in the SiFive PLIC driver
- Make the unmapped event handling in the TI SCI driver work
correctly
- A few minor fixes and cleanups in various chip drivers and Kconfig"
* tag 'irq-urgent-2020-11-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
dt-bindings: irqchip: ti, sci-inta: Fix diagram indentation for unmapped events
irqchip/ti-sci-inta: Add support for unmapped event handling
dt-bindings: irqchip: ti, sci-inta: Update for unmapped event handling
irqchip/renesas-intc-irqpin: Merge irlm_bit and needs_irlm
irqchip/sifive-plic: Fix chip_data access within a hierarchy
irqchip/sifive-plic: Fix broken irq_set_affinity() callback
irqchip/stm32-exti: Add all LP timer exti direct events support
irqchip/bcm2836: Fix missing __init annotation
irqchip/mips: Drop selection of IRQ_DOMAIN_HIERARCHY
irqchip/mst: Make mst_intc_of_init static
irqchip/mst: MST_IRQ should depend on ARCH_MEDIATEK or ARCH_MSTARV7
genirq: Let GENERIC_IRQ_IPI select IRQ_DOMAIN_HIERARCHY
111 lines
4.0 KiB
YAML
111 lines
4.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-inta.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Texas Instruments K3 Interrupt Aggregator
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maintainers:
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- Lokesh Vutla <lokeshvutla@ti.com>
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allOf:
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- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
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description: |
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The Interrupt Aggregator (INTA) provides a centralized machine
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which handles the termination of system events to that they can
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be coherently processed by the host(s) in the system. A maximum
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of 64 events can be mapped to a single interrupt.
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Interrupt Aggregator
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+-----------------------------------------+
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| Intmap VINT |
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| +--------------+ +------------+ |
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m ------>| | vint | bit | | 0 |.....|63| vint0 |
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. | +--------------+ +------------+ | +------+
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. | . . | | HOST |
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Globalevents ------>| . . |----->| IRQ |
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. | . . | | CTRL |
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. | . . | +------+
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n ------>| +--------------+ +------------+ |
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| | vint | bit | | 0 |.....|63| vintx |
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| +--------------+ +------------+ |
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| |
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| Unmap |
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| +--------------+ |
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Unmapped events ---->| | umapidx |-------------------------> Globalevents
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| +--------------+ |
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+-----------------------------------------+
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Configuration of these Intmap registers that maps global events to vint is
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done by a system controller (like the Device Memory and Security Controller
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on AM654 SoC). Driver should request the system controller to get the range
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of global events and vints assigned to the requesting host. Management
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of these requested resources should be handled by driver and requests
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system controller to map specific global event to vint, bit pair.
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Communication between the host processor running an OS and the system
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controller happens through a protocol called TI System Control Interface
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(TISCI protocol).
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properties:
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compatible:
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const: ti,sci-inta
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reg:
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maxItems: 1
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interrupt-controller: true
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msi-controller: true
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ti,interrupt-ranges:
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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description: |
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Interrupt ranges that converts the INTA output hw irq numbers
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to parents's input interrupt numbers.
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items:
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items:
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- description: |
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"output_irq" specifies the base for inta output irq
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- description: |
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"parent's input irq" specifies the base for parent irq
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- description: |
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"limit" specifies the limit for translation
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ti,unmapped-event-sources:
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$ref: /schemas/types.yaml#definitions/phandle-array
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description:
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Array of phandles to DMA controllers where the unmapped events originate.
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required:
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- compatible
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- reg
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- interrupt-controller
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- msi-controller
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- ti,sci
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- ti,sci-dev-id
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- ti,interrupt-ranges
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unevaluatedProperties: false
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examples:
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- |
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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main_udmass_inta: msi-controller@33d00000 {
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compatible = "ti,sci-inta";
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reg = <0x0 0x33d00000 0x0 0x100000>;
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interrupt-controller;
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msi-controller;
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interrupt-parent = <&main_navss_intr>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <179>;
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ti,interrupt-ranges = <0 0 256>;
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};
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};
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