814eae5982
The introduction of {map/swizzle}_irq() hooks in the struct pci_host_bridge
allowed to replace the pci_fixup_irqs() PCI IRQ allocation in alpha arch
PCI code with per-bridge map/swizzle functions with commit 0e4c2eeb75
("alpha/PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping
hooks").
As a side effect of converting PCI IRQ allocation to the struct
pci_host_bridge {map/swizzle}_irq() hooks mechanism, the actual PCI IRQ
allocation function (ie pci_assign_irq()) is carried out per-device in
pci_device_probe() that is called when a PCI device driver is about to be
probed.
This means that, for drivers compiled as loadable modules, the actual PCI
device IRQ allocation can now happen after the system has booted so the
struct pci_host_bridge {map/swizzle}_irq() hooks pci_assign_irq() relies on
must stay valid after the system has booted so that PCI core can carry out
PCI IRQ allocation correctly.
Most of the alpha board structures pci_map_irq() and pci_swizzle() hooks
(that are used to initialize their struct pci_host_bridge equivalent
through the alpha_mv global variable - that represents the struct
alpha_machine_vector of the running kernel) are marked as
__init/__initdata; this causes freed memory dereferences when PCI IRQ
allocation is carried out after the kernel has booted (ie when loading PCI
drivers as loadable module) because when the kernel tries to bind the PCI
device to its (module) driver, the function pci_assign_irq() is called,
that in turn retrieves the struct pci_host_bridge {map/swizzle}_irq() hooks
to carry out PCI IRQ allocation; if those hooks are marked as __init
code/__initdata they point at freed/invalid memory.
Fix the issue by removing the __init/__initdata markers from all subarch
struct alpha_machine_vector.pci_map_irq()/pci_swizzle() functions (and
data).
Fixes: 0e4c2eeb75 ("alpha/PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooks")
Link: http://lkml.kernel.org/r/alpine.LRH.2.21.1710251043170.7098@math.ut.ee
Reported-by: Meelis Roos <mroos@linux.ee>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
Cc: Meelis Roos <mroos@linux.ee>
Cc: Matt Turner <mattst88@gmail.com>
462 lines
12 KiB
C
462 lines
12 KiB
C
/*
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* linux/arch/alpha/kernel/sys_sio.c
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*
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* Copyright (C) 1995 David A Rusling
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* Copyright (C) 1996 Jay A Estabrook
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* Copyright (C) 1998, 1999 Richard Henderson
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*
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* Code for all boards that route the PCI interrupts through the SIO
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* PCI/ISA bridge. This includes Noname (AXPpci33), Multia (UDB),
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* Kenetics's Platform 2000, Avanti (AlphaStation), XL, and AlphaBook1.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/screen_info.h>
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#include <asm/compiler.h>
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#include <asm/ptrace.h>
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#include <asm/dma.h>
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#include <asm/irq.h>
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#include <asm/mmu_context.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/core_apecs.h>
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#include <asm/core_lca.h>
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#include <asm/tlbflush.h>
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#include "proto.h"
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#include "irq_impl.h"
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#include "pci_impl.h"
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#include "machvec_impl.h"
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#include "pc873xx.h"
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#if defined(ALPHA_RESTORE_SRM_SETUP)
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/* Save LCA configuration data as the console had it set up. */
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struct
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{
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unsigned int orig_route_tab; /* for SAVE/RESTORE */
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} saved_config __attribute((common));
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#endif
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static void __init
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sio_init_irq(void)
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{
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if (alpha_using_srm)
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alpha_mv.device_interrupt = srm_device_interrupt;
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init_i8259a_irqs();
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common_init_isa_dma();
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}
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static inline void __init
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alphabook1_init_arch(void)
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{
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/* The AlphaBook1 has LCD video fixed at 800x600,
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37 rows and 100 cols. */
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screen_info.orig_y = 37;
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screen_info.orig_video_cols = 100;
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screen_info.orig_video_lines = 37;
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lca_init_arch();
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}
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/*
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* sio_route_tab selects irq routing in PCI/ISA bridge so that:
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* PIRQ0 -> irq 15
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* PIRQ1 -> irq 9
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* PIRQ2 -> irq 10
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* PIRQ3 -> irq 11
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*
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* This probably ought to be configurable via MILO. For
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* example, sound boards seem to like using IRQ 9.
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*
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* This is NOT how we should do it. PIRQ0-X should have
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* their own IRQs, the way intel uses the IO-APIC IRQs.
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*/
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static void __init
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sio_pci_route(void)
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{
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unsigned int orig_route_tab;
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/* First, ALWAYS read and print the original setting. */
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pci_bus_read_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
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&orig_route_tab);
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printk("%s: PIRQ original 0x%x new 0x%x\n", __func__,
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orig_route_tab, alpha_mv.sys.sio.route_tab);
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#if defined(ALPHA_RESTORE_SRM_SETUP)
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saved_config.orig_route_tab = orig_route_tab;
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#endif
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/* Now override with desired setting. */
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pci_bus_write_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
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alpha_mv.sys.sio.route_tab);
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}
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static unsigned int __init
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sio_collect_irq_levels(void)
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{
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unsigned int level_bits = 0;
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struct pci_dev *dev = NULL;
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/* Iterate through the devices, collecting IRQ levels. */
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for_each_pci_dev(dev) {
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if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) &&
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(dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA))
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continue;
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if (dev->irq)
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level_bits |= (1 << dev->irq);
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}
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return level_bits;
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}
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static void __init
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sio_fixup_irq_levels(unsigned int level_bits)
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{
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unsigned int old_level_bits;
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/*
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* Now, make all PCI interrupts level sensitive. Notice:
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* these registers must be accessed byte-wise. inw()/outw()
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* don't work.
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*
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* Make sure to turn off any level bits set for IRQs 9,10,11,15,
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* so that the only bits getting set are for devices actually found.
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* Note that we do preserve the remainder of the bits, which we hope
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* will be set correctly by ARC/SRM.
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*
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* Note: we at least preserve any level-set bits on AlphaBook1
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*/
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old_level_bits = inb(0x4d0) | (inb(0x4d1) << 8);
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level_bits |= (old_level_bits & 0x71ff);
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outb((level_bits >> 0) & 0xff, 0x4d0);
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outb((level_bits >> 8) & 0xff, 0x4d1);
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}
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static inline int
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noname_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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/*
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* The Noname board has 5 PCI slots with each of the 4
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* interrupt pins routed to different pins on the PCI/ISA
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* bridge (PIRQ0-PIRQ3). The table below is based on
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* information available at:
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*
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* http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt
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*
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* I have no information on the Avanti interrupt routing, but
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* the routing seems to be identical to the Noname except
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* that the Avanti has an additional slot whose routing I'm
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* unsure of.
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*
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* pirq_tab[0] is a fake entry to deal with old PCI boards
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* that have the interrupt pin number hardwired to 0 (meaning
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* that they use the default INTA line, if they are interrupt
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* driven at all).
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*/
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static char irq_tab[][5] = {
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/*INT A B C D */
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{ 3, 3, 3, 3, 3}, /* idsel 6 (53c810) */
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{-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */
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{ 2, 2, -1, -1, -1}, /* idsel 8 (Hack: slot closest ISA) */
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{-1, -1, -1, -1, -1}, /* idsel 9 (unused) */
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{-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
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{ 0, 0, 2, 1, 0}, /* idsel 11 KN25_PCI_SLOT0 */
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{ 1, 1, 0, 2, 1}, /* idsel 12 KN25_PCI_SLOT1 */
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{ 2, 2, 1, 0, 2}, /* idsel 13 KN25_PCI_SLOT2 */
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{ 0, 0, 0, 0, 0}, /* idsel 14 AS255 TULIP */
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};
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const long min_idsel = 6, max_idsel = 14, irqs_per_slot = 5;
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int irq = COMMON_TABLE_LOOKUP, tmp;
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tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
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return irq >= 0 ? tmp : -1;
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}
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static inline int
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p2k_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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static char irq_tab[][5] = {
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/*INT A B C D */
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{ 0, 0, -1, -1, -1}, /* idsel 6 (53c810) */
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{-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */
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{ 1, 1, 2, 3, 0}, /* idsel 8 (slot A) */
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{ 2, 2, 3, 0, 1}, /* idsel 9 (slot B) */
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{-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
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{-1, -1, -1, -1, -1}, /* idsel 11 (unused) */
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{ 3, 3, -1, -1, -1}, /* idsel 12 (CMD0646) */
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};
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const long min_idsel = 6, max_idsel = 12, irqs_per_slot = 5;
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int irq = COMMON_TABLE_LOOKUP, tmp;
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tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
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return irq >= 0 ? tmp : -1;
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}
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static inline void __init
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noname_init_pci(void)
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{
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common_init_pci();
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sio_pci_route();
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sio_fixup_irq_levels(sio_collect_irq_levels());
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if (pc873xx_probe() == -1) {
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printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n");
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} else {
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printk(KERN_INFO "Found %s Super IO chip at 0x%x\n",
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pc873xx_get_model(), pc873xx_get_base());
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/* Enabling things in the Super IO chip doesn't actually
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* configure and enable things, the legacy drivers still
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* need to do the actual configuration and enabling.
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* This only unblocks them.
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*/
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#if !defined(CONFIG_ALPHA_AVANTI)
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/* Don't bother on the Avanti family.
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* None of them had on-board IDE.
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*/
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pc873xx_enable_ide();
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#endif
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pc873xx_enable_epp19();
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}
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}
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static inline void __init
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alphabook1_init_pci(void)
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{
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struct pci_dev *dev;
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unsigned char orig, config;
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common_init_pci();
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sio_pci_route();
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/*
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* On the AlphaBook1, the PCMCIA chip (Cirrus 6729)
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* is sensitive to PCI bus bursts, so we must DISABLE
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* burst mode for the NCR 8xx SCSI... :-(
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*
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* Note that the NCR810 SCSI driver must preserve the
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* setting of the bit in order for this to work. At the
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* moment (2.0.29), ncr53c8xx.c does NOT do this, but
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* 53c7,8xx.c DOES.
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*/
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dev = NULL;
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while ((dev = pci_get_device(PCI_VENDOR_ID_NCR, PCI_ANY_ID, dev))) {
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if (dev->device == PCI_DEVICE_ID_NCR_53C810
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|| dev->device == PCI_DEVICE_ID_NCR_53C815
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|| dev->device == PCI_DEVICE_ID_NCR_53C820
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|| dev->device == PCI_DEVICE_ID_NCR_53C825) {
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unsigned long io_port;
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unsigned char ctest4;
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io_port = dev->resource[0].start;
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ctest4 = inb(io_port+0x21);
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if (!(ctest4 & 0x80)) {
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printk("AlphaBook1 NCR init: setting"
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" burst disable\n");
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outb(ctest4 | 0x80, io_port+0x21);
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}
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}
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}
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/* Do not set *ANY* level triggers for AlphaBook1. */
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sio_fixup_irq_levels(0);
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/* Make sure that register PR1 indicates 1Mb mem */
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outb(0x0f, 0x3ce); orig = inb(0x3cf); /* read PR5 */
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outb(0x0f, 0x3ce); outb(0x05, 0x3cf); /* unlock PR0-4 */
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outb(0x0b, 0x3ce); config = inb(0x3cf); /* read PR1 */
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if ((config & 0xc0) != 0xc0) {
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printk("AlphaBook1 VGA init: setting 1Mb memory\n");
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config |= 0xc0;
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outb(0x0b, 0x3ce); outb(config, 0x3cf); /* write PR1 */
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}
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outb(0x0f, 0x3ce); outb(orig, 0x3cf); /* (re)lock PR0-4 */
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}
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void
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sio_kill_arch(int mode)
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{
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#if defined(ALPHA_RESTORE_SRM_SETUP)
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/* Since we cannot read the PCI DMA Window CSRs, we
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* cannot restore them here.
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*
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* However, we CAN read the PIRQ route register, so restore it
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* now...
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*/
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pci_bus_write_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
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saved_config.orig_route_tab);
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#endif
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}
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/*
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* The System Vectors
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*/
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#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_BOOK1)
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struct alpha_machine_vector alphabook1_mv __initmv = {
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.vector_name = "AlphaBook1",
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DO_EV4_MMU,
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DO_DEFAULT_RTC,
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DO_LCA_IO,
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.machine_check = lca_machine_check,
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
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.min_io_address = DEFAULT_IO_BASE,
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.min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
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.nr_irqs = 16,
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.device_interrupt = isa_device_interrupt,
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.init_arch = alphabook1_init_arch,
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.init_irq = sio_init_irq,
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.init_rtc = common_init_rtc,
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.init_pci = alphabook1_init_pci,
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.kill_arch = sio_kill_arch,
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.pci_map_irq = noname_map_irq,
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.pci_swizzle = common_swizzle,
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.sys = { .sio = {
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/* NCR810 SCSI is 14, PCMCIA controller is 15. */
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.route_tab = 0x0e0f0a0a,
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}}
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};
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ALIAS_MV(alphabook1)
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#endif
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#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_AVANTI)
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struct alpha_machine_vector avanti_mv __initmv = {
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.vector_name = "Avanti",
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DO_EV4_MMU,
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DO_DEFAULT_RTC,
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DO_APECS_IO,
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.machine_check = apecs_machine_check,
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
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.min_io_address = DEFAULT_IO_BASE,
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.min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
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.nr_irqs = 16,
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.device_interrupt = isa_device_interrupt,
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.init_arch = apecs_init_arch,
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.init_irq = sio_init_irq,
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.init_rtc = common_init_rtc,
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.init_pci = noname_init_pci,
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.kill_arch = sio_kill_arch,
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.pci_map_irq = noname_map_irq,
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.pci_swizzle = common_swizzle,
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.sys = { .sio = {
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.route_tab = 0x0b0a050f, /* leave 14 for IDE, 9 for SND */
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}}
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};
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ALIAS_MV(avanti)
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#endif
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#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_NONAME)
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struct alpha_machine_vector noname_mv __initmv = {
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.vector_name = "Noname",
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DO_EV4_MMU,
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DO_DEFAULT_RTC,
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DO_LCA_IO,
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.machine_check = lca_machine_check,
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
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.min_io_address = DEFAULT_IO_BASE,
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.min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
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.nr_irqs = 16,
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.device_interrupt = srm_device_interrupt,
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.init_arch = lca_init_arch,
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.init_irq = sio_init_irq,
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.init_rtc = common_init_rtc,
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.init_pci = noname_init_pci,
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.kill_arch = sio_kill_arch,
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.pci_map_irq = noname_map_irq,
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.pci_swizzle = common_swizzle,
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.sys = { .sio = {
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/* For UDB, the only available PCI slot must not map to IRQ 9,
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since that's the builtin MSS sound chip. That PCI slot
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will map to PIRQ1 (for INTA at least), so we give it IRQ 15
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instead.
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Unfortunately we have to do this for NONAME as well, since
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they are co-indicated when the platform type "Noname" is
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selected... :-( */
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.route_tab = 0x0b0a0f0d,
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}}
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};
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ALIAS_MV(noname)
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#endif
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#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_P2K)
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struct alpha_machine_vector p2k_mv __initmv = {
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.vector_name = "Platform2000",
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DO_EV4_MMU,
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DO_DEFAULT_RTC,
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DO_LCA_IO,
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.machine_check = lca_machine_check,
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.max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
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.min_io_address = DEFAULT_IO_BASE,
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.min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
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.nr_irqs = 16,
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.device_interrupt = srm_device_interrupt,
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.init_arch = lca_init_arch,
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.init_irq = sio_init_irq,
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.init_rtc = common_init_rtc,
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.init_pci = noname_init_pci,
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.kill_arch = sio_kill_arch,
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.pci_map_irq = p2k_map_irq,
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.pci_swizzle = common_swizzle,
|
|
|
|
.sys = { .sio = {
|
|
.route_tab = 0x0b0a090f,
|
|
}}
|
|
};
|
|
ALIAS_MV(p2k)
|
|
#endif
|
|
|
|
#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_XL)
|
|
struct alpha_machine_vector xl_mv __initmv = {
|
|
.vector_name = "XL",
|
|
DO_EV4_MMU,
|
|
DO_DEFAULT_RTC,
|
|
DO_APECS_IO,
|
|
.machine_check = apecs_machine_check,
|
|
.max_isa_dma_address = ALPHA_XL_MAX_ISA_DMA_ADDRESS,
|
|
.min_io_address = DEFAULT_IO_BASE,
|
|
.min_mem_address = XL_DEFAULT_MEM_BASE,
|
|
|
|
.nr_irqs = 16,
|
|
.device_interrupt = isa_device_interrupt,
|
|
|
|
.init_arch = apecs_init_arch,
|
|
.init_irq = sio_init_irq,
|
|
.init_rtc = common_init_rtc,
|
|
.init_pci = noname_init_pci,
|
|
.kill_arch = sio_kill_arch,
|
|
.pci_map_irq = noname_map_irq,
|
|
.pci_swizzle = common_swizzle,
|
|
|
|
.sys = { .sio = {
|
|
.route_tab = 0x0b0a090f,
|
|
}}
|
|
};
|
|
ALIAS_MV(xl)
|
|
#endif
|