814eae5982
The introduction of {map/swizzle}_irq() hooks in the struct pci_host_bridge
allowed to replace the pci_fixup_irqs() PCI IRQ allocation in alpha arch
PCI code with per-bridge map/swizzle functions with commit 0e4c2eeb75
("alpha/PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping
hooks").
As a side effect of converting PCI IRQ allocation to the struct
pci_host_bridge {map/swizzle}_irq() hooks mechanism, the actual PCI IRQ
allocation function (ie pci_assign_irq()) is carried out per-device in
pci_device_probe() that is called when a PCI device driver is about to be
probed.
This means that, for drivers compiled as loadable modules, the actual PCI
device IRQ allocation can now happen after the system has booted so the
struct pci_host_bridge {map/swizzle}_irq() hooks pci_assign_irq() relies on
must stay valid after the system has booted so that PCI core can carry out
PCI IRQ allocation correctly.
Most of the alpha board structures pci_map_irq() and pci_swizzle() hooks
(that are used to initialize their struct pci_host_bridge equivalent
through the alpha_mv global variable - that represents the struct
alpha_machine_vector of the running kernel) are marked as
__init/__initdata; this causes freed memory dereferences when PCI IRQ
allocation is carried out after the kernel has booted (ie when loading PCI
drivers as loadable module) because when the kernel tries to bind the PCI
device to its (module) driver, the function pci_assign_irq() is called,
that in turn retrieves the struct pci_host_bridge {map/swizzle}_irq() hooks
to carry out PCI IRQ allocation; if those hooks are marked as __init
code/__initdata they point at freed/invalid memory.
Fix the issue by removing the __init/__initdata markers from all subarch
struct alpha_machine_vector.pci_map_irq()/pci_swizzle() functions (and
data).
Fixes: 0e4c2eeb75 ("alpha/PCI: Replace pci_fixup_irqs() call with host bridge IRQ mapping hooks")
Link: http://lkml.kernel.org/r/alpine.LRH.2.21.1710251043170.7098@math.ut.ee
Reported-by: Meelis Roos <mroos@linux.ee>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
Cc: Meelis Roos <mroos@linux.ee>
Cc: Matt Turner <mattst88@gmail.com>
240 lines
5.8 KiB
C
240 lines
5.8 KiB
C
/*
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* linux/arch/alpha/kernel/sys_ruffian.c
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*
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* Copyright (C) 1995 David A Rusling
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* Copyright (C) 1996 Jay A Estabrook
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* Copyright (C) 1998, 1999, 2000 Richard Henderson
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*
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* Code supporting the RUFFIAN.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/ioport.h>
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#include <linux/timex.h>
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#include <linux/init.h>
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#include <asm/ptrace.h>
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#include <asm/dma.h>
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#include <asm/irq.h>
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#include <asm/mmu_context.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/core_cia.h>
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#include <asm/tlbflush.h>
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#include "proto.h"
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#include "irq_impl.h"
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#include "pci_impl.h"
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#include "machvec_impl.h"
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static void __init
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ruffian_init_irq(void)
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{
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/* Invert 6&7 for i82371 */
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*(vulp)PYXIS_INT_HILO = 0x000000c0UL; mb();
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*(vulp)PYXIS_INT_CNFG = 0x00002064UL; mb(); /* all clear */
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outb(0x11,0xA0);
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outb(0x08,0xA1);
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outb(0x02,0xA1);
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outb(0x01,0xA1);
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outb(0xFF,0xA1);
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outb(0x11,0x20);
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outb(0x00,0x21);
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outb(0x04,0x21);
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outb(0x01,0x21);
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outb(0xFF,0x21);
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/* Finish writing the 82C59A PIC Operation Control Words */
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outb(0x20,0xA0);
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outb(0x20,0x20);
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init_i8259a_irqs();
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/* Not interested in the bogus interrupts (0,3,6),
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NMI (1), HALT (2), flash (5), or 21142 (8). */
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init_pyxis_irqs(0x16f0000);
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common_init_isa_dma();
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}
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#define RUFFIAN_LATCH DIV_ROUND_CLOSEST(PIT_TICK_RATE, HZ)
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static void __init
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ruffian_init_rtc(void)
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{
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/* Ruffian does not have the RTC connected to the CPU timer
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interrupt. Instead, it uses the PIT connected to IRQ 0. */
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/* Setup interval timer. */
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outb(0x34, 0x43); /* binary, mode 2, LSB/MSB, ch 0 */
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outb(RUFFIAN_LATCH & 0xff, 0x40); /* LSB */
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outb(RUFFIAN_LATCH >> 8, 0x40); /* MSB */
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outb(0xb6, 0x43); /* pit counter 2: speaker */
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outb(0x31, 0x42);
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outb(0x13, 0x42);
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setup_irq(0, &timer_irqaction);
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}
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static void
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ruffian_kill_arch (int mode)
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{
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cia_kill_arch(mode);
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#if 0
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/* This only causes re-entry to ARCSBIOS */
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/* Perhaps this works for other PYXIS as well? */
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*(vuip) PYXIS_RESET = 0x0000dead;
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mb();
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#endif
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}
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/*
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* Interrupt routing:
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*
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* Primary bus
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* IdSel INTA INTB INTC INTD
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* 21052 13 - - - -
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* SIO 14 23 - - -
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* 21143 15 44 - - -
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* Slot 0 17 43 42 41 40
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*
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* Secondary bus
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* IdSel INTA INTB INTC INTD
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* Slot 0 8 (18) 19 18 17 16
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* Slot 1 9 (19) 31 30 29 28
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* Slot 2 10 (20) 27 26 25 24
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* Slot 3 11 (21) 39 38 37 36
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* Slot 4 12 (22) 35 34 33 32
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* 53c875 13 (23) 20 - - -
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*
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*/
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static int
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ruffian_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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static char irq_tab[11][5] = {
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/*INT INTA INTB INTC INTD */
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{-1, -1, -1, -1, -1}, /* IdSel 13, 21052 */
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{-1, -1, -1, -1, -1}, /* IdSel 14, SIO */
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{44, 44, 44, 44, 44}, /* IdSel 15, 21143 */
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{-1, -1, -1, -1, -1}, /* IdSel 16, none */
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{43, 43, 42, 41, 40}, /* IdSel 17, 64-bit slot */
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/* the next 6 are actually on PCI bus 1, across the bridge */
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{19, 19, 18, 17, 16}, /* IdSel 8, slot 0 */
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{31, 31, 30, 29, 28}, /* IdSel 9, slot 1 */
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{27, 27, 26, 25, 24}, /* IdSel 10, slot 2 */
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{39, 39, 38, 37, 36}, /* IdSel 11, slot 3 */
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{35, 35, 34, 33, 32}, /* IdSel 12, slot 4 */
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{20, 20, 20, 20, 20}, /* IdSel 13, 53c875 */
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};
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const long min_idsel = 13, max_idsel = 23, irqs_per_slot = 5;
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return COMMON_TABLE_LOOKUP;
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}
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static u8
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ruffian_swizzle(struct pci_dev *dev, u8 *pinp)
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{
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int slot, pin = *pinp;
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if (dev->bus->number == 0) {
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slot = PCI_SLOT(dev->devfn);
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}
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/* Check for the built-in bridge. */
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else if (PCI_SLOT(dev->bus->self->devfn) == 13) {
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slot = PCI_SLOT(dev->devfn) + 10;
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}
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else
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{
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/* Must be a card-based bridge. */
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do {
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if (PCI_SLOT(dev->bus->self->devfn) == 13) {
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slot = PCI_SLOT(dev->devfn) + 10;
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break;
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}
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pin = pci_swizzle_interrupt_pin(dev, pin);
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/* Move up the chain of bridges. */
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dev = dev->bus->self;
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/* Slot of the next bridge. */
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slot = PCI_SLOT(dev->devfn);
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} while (dev->bus->self);
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}
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*pinp = pin;
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return slot;
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}
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#ifdef BUILDING_FOR_MILO
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/*
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* The DeskStation Ruffian motherboard firmware does not place
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* the memory size in the PALimpure area. Therefore, we use
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* the Bank Configuration Registers in PYXIS to obtain the size.
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*/
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static unsigned long __init
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ruffian_get_bank_size(unsigned long offset)
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{
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unsigned long bank_addr, bank, ret = 0;
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/* Valid offsets are: 0x800, 0x840 and 0x880
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since Ruffian only uses three banks. */
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bank_addr = (unsigned long)PYXIS_MCR + offset;
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bank = *(vulp)bank_addr;
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/* Check BANK_ENABLE */
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if (bank & 0x01) {
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static unsigned long size[] __initdata = {
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0x40000000UL, /* 0x00, 1G */
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0x20000000UL, /* 0x02, 512M */
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0x10000000UL, /* 0x04, 256M */
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0x08000000UL, /* 0x06, 128M */
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0x04000000UL, /* 0x08, 64M */
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0x02000000UL, /* 0x0a, 32M */
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0x01000000UL, /* 0x0c, 16M */
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0x00800000UL, /* 0x0e, 8M */
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0x80000000UL, /* 0x10, 2G */
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};
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bank = (bank & 0x1e) >> 1;
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if (bank < ARRAY_SIZE(size))
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ret = size[bank];
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}
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return ret;
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}
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#endif /* BUILDING_FOR_MILO */
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/*
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* The System Vector
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*/
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struct alpha_machine_vector ruffian_mv __initmv = {
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.vector_name = "Ruffian",
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DO_EV5_MMU,
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DO_DEFAULT_RTC,
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DO_PYXIS_IO,
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.machine_check = cia_machine_check,
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.max_isa_dma_address = ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS,
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.min_io_address = DEFAULT_IO_BASE,
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.min_mem_address = DEFAULT_MEM_BASE,
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.pci_dac_offset = PYXIS_DAC_OFFSET,
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.nr_irqs = 48,
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.device_interrupt = pyxis_device_interrupt,
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.init_arch = pyxis_init_arch,
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.init_irq = ruffian_init_irq,
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.init_rtc = ruffian_init_rtc,
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.init_pci = cia_init_pci,
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.kill_arch = ruffian_kill_arch,
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.pci_map_irq = ruffian_map_irq,
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.pci_swizzle = ruffian_swizzle,
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};
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ALIAS_MV(ruffian)
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