3c75a6fb7f
Cortex-A510 erratum 2454944 may cause clean cache lines to be erroneously written back to memory, breaking the assumptions we rely on for non-coherent DMA. Try to mitigate this by implementing special DMA ops that do their best to avoid cacheable aliases via a combination of bounce-buffering and manipulating the linear map directly, to minimise the chance of DMA-mapped pages being speculated back into caches. The other main concern is initial entry, where cache lines covering the kernel image might potentially become affected between being cleaned by the bootloader and the kernel being called, which might require additional cache maintenance from the bootloader to be safe in that regard too. Cortex-A510 supports S2FWB, so KVM should be unaffected. For the workaround to be applied, it needs to be explicitly requested through dedicated arm64_noalias_setup_dma_ops callback. Bug: 223346425 (cherry picked from commit 683efc5fc6eeb653caf85c33a2fb92a33c8faa75 https://git.gitlab.arm.com/linux-arm/linux-rm.git arm64/2454944-dev) Change-Id: If76b97dc39c278edb80f9b750129975ab2ac563e Signed-off-by: Robin Murphy <robin.murphy@arm.com> [BM: Stripping-down the original solution by removing support for cpu capabilities and ammending relevant bits, with the final version being reduced to dedicated DMA ops with dependencies on rodata_full being enabled (CONFIG_RODATA_FULL_DEFAULT_ENABLED), swiotlb late init and disabling lazy tlb flushing. Also, as a consequence, reducing debugging support.] Signed-off-by: Beata Michalska <beata.michalska@arm.com>
16 lines
375 B
C
16 lines
375 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2022-2023 ARM Ltd.
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*/
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#ifndef __ASM_DMA_MAPPING_NOALIAS_H
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#define __ASM_DMA_MAPPING_NOALIAS_H
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#ifdef CONFIG_ARM64_ERRATUM_2454944
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void arm64_noalias_setup_dma_ops(struct device *dev);
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#else
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static inline void arm64_noalias_setup_dma_ops(struct device *dev)
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{
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}
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#endif
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#endif /* __ASM_DMA_MAPPING_NOALIAS_H */
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