d84f6269ce
In case of driver probe and pm resume we need to check that the cryptocell hardware reset cycle is completed. during the reset cycle that Cryptocell provide read only access to the APB interface which allows to verify through the CC registers that the reset is completed. Until reset completion we assume that any write/crypto operation is blocked. Signed-off-by: Ofir Drang <ofir.drang@arm.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
130 lines
3.0 KiB
C
130 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/pm_runtime.h>
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#include "cc_driver.h"
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#include "cc_buffer_mgr.h"
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#include "cc_request_mgr.h"
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#include "cc_sram_mgr.h"
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#include "cc_ivgen.h"
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#include "cc_hash.h"
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#include "cc_pm.h"
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#include "cc_fips.h"
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#define POWER_DOWN_ENABLE 0x01
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#define POWER_DOWN_DISABLE 0x00
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const struct dev_pm_ops ccree_pm = {
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SET_RUNTIME_PM_OPS(cc_pm_suspend, cc_pm_resume, NULL)
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};
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int cc_pm_suspend(struct device *dev)
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{
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struct cc_drvdata *drvdata = dev_get_drvdata(dev);
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int rc;
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dev_dbg(dev, "set HOST_POWER_DOWN_EN\n");
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rc = cc_suspend_req_queue(drvdata);
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if (rc) {
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dev_err(dev, "cc_suspend_req_queue (%x)\n", rc);
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return rc;
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}
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fini_cc_regs(drvdata);
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cc_iowrite(drvdata, CC_REG(HOST_POWER_DOWN_EN), POWER_DOWN_ENABLE);
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cc_clk_off(drvdata);
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return 0;
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}
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int cc_pm_resume(struct device *dev)
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{
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int rc;
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struct cc_drvdata *drvdata = dev_get_drvdata(dev);
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dev_dbg(dev, "unset HOST_POWER_DOWN_EN\n");
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/* Enables the device source clk */
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rc = cc_clk_on(drvdata);
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if (rc) {
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dev_err(dev, "failed getting clock back on. We're toast.\n");
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return rc;
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}
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/* wait for Crytpcell reset completion */
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if (!cc_wait_for_reset_completion(drvdata)) {
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dev_err(dev, "Cryptocell reset not completed");
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return -EBUSY;
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}
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cc_iowrite(drvdata, CC_REG(HOST_POWER_DOWN_EN), POWER_DOWN_DISABLE);
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rc = init_cc_regs(drvdata, false);
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if (rc) {
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dev_err(dev, "init_cc_regs (%x)\n", rc);
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return rc;
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}
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/* check if tee fips error occurred during power down */
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cc_tee_handle_fips_error(drvdata);
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rc = cc_resume_req_queue(drvdata);
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if (rc) {
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dev_err(dev, "cc_resume_req_queue (%x)\n", rc);
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return rc;
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}
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/* must be after the queue resuming as it uses the HW queue*/
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cc_init_hash_sram(drvdata);
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cc_init_iv_sram(drvdata);
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return 0;
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}
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int cc_pm_get(struct device *dev)
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{
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int rc = 0;
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struct cc_drvdata *drvdata = dev_get_drvdata(dev);
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if (cc_req_queue_suspended(drvdata))
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rc = pm_runtime_get_sync(dev);
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else
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pm_runtime_get_noresume(dev);
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return rc;
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}
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int cc_pm_put_suspend(struct device *dev)
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{
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int rc = 0;
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struct cc_drvdata *drvdata = dev_get_drvdata(dev);
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if (!cc_req_queue_suspended(drvdata)) {
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pm_runtime_mark_last_busy(dev);
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rc = pm_runtime_put_autosuspend(dev);
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} else {
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/* Something wrong happens*/
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dev_err(dev, "request to suspend already suspended queue");
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rc = -EBUSY;
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}
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return rc;
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}
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int cc_pm_init(struct cc_drvdata *drvdata)
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{
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struct device *dev = drvdata_to_dev(drvdata);
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/* must be before the enabling to avoid resdundent suspending */
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pm_runtime_set_autosuspend_delay(dev, CC_SUSPEND_TIMEOUT);
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pm_runtime_use_autosuspend(dev);
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/* activate the PM module */
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return pm_runtime_set_active(dev);
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}
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/* enable the PM module*/
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void cc_pm_go(struct cc_drvdata *drvdata)
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{
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pm_runtime_enable(drvdata_to_dev(drvdata));
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}
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void cc_pm_fini(struct cc_drvdata *drvdata)
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{
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pm_runtime_disable(drvdata_to_dev(drvdata));
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}
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