
Add R-Car D3 (R8A77995) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen3 CPG code. Based on the R-Car Series, 3rd Generation Hardware User's Manual, Rev. 0.55, Jun. 30, 2017. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Rob Herring <robh@kernel.org>
28 lines
1.0 KiB
Makefile
28 lines
1.0 KiB
Makefile
# SoC
|
|
obj-$(CONFIG_CLK_EMEV2) += clk-emev2.o
|
|
obj-$(CONFIG_CLK_RZA1) += clk-rz.o
|
|
obj-$(CONFIG_CLK_R8A73A4) += clk-r8a73a4.o
|
|
obj-$(CONFIG_CLK_R8A7740) += clk-r8a7740.o
|
|
obj-$(CONFIG_CLK_R8A7743) += r8a7743-cpg-mssr.o
|
|
obj-$(CONFIG_CLK_R8A7745) += r8a7745-cpg-mssr.o
|
|
obj-$(CONFIG_CLK_R8A7778) += clk-r8a7778.o
|
|
obj-$(CONFIG_CLK_R8A7779) += clk-r8a7779.o
|
|
obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
|
|
obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o
|
|
obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
|
|
obj-$(CONFIG_CLK_R8A7794) += r8a7794-cpg-mssr.o
|
|
obj-$(CONFIG_CLK_R8A7795) += r8a7795-cpg-mssr.o
|
|
obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o
|
|
obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o
|
|
obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
|
|
|
|
# Family
|
|
obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o
|
|
obj-$(CONFIG_CLK_RCAR_GEN2_CPG) += rcar-gen2-cpg.o
|
|
obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o
|
|
|
|
# Generic
|
|
obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o
|
|
obj-$(CONFIG_CLK_RENESAS_CPG_MSTP) += clk-mstp.o
|
|
obj-$(CONFIG_CLK_RENESAS_DIV6) += clk-div6.o
|