xiaomi-sm8450/android_kernel_xiaomi_sm8450
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android_kernel_xiaomi_sm8450/arch/mips/mm/sc-mips.c
Kevin Cernekee 96983ffefc MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines. 
This extends commit a8ca8b64e3 to cover
MIPSxx-style board cache code.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2009-09-30 21:47:00 +02:00

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