e1ac611f57
Convert the generic PCI host binding to DT schema. The derivative Juno, PLDA XpressRICH3-AXI, and Designware ECAM bindings all just vary in their compatible strings. The simplest way to convert those to schema is just add them into the common generic PCI host schema. The HiSilicon ECAM and Cavium ThunderX PEM bindings have an additional 'reg' entry, but are otherwise the same binding as well. Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Andrew Murray <andrew.murray@arm.com> Cc: Zhou Wang <wangzhou1@hisilicon.com> Cc: Will Deacon <will@kernel.org> Cc: David Daney <david.daney@cavium.com> Signed-off-by: Rob Herring <robh@kernel.org>
44 lines
1.5 KiB
Plaintext
44 lines
1.5 KiB
Plaintext
HiSilicon Hip05 and Hip06 PCIe host bridge DT description
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HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core.
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It shares common functions with the PCIe DesignWare core driver and inherits
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common properties defined in
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Documentation/devicetree/bindings/pci/designware-pcie.txt.
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Additional properties are described here:
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Required properties
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- compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
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- reg: Should contain rc_dbi, config registers location and length.
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- reg-names: Must include the following entries:
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"rc_dbi": controller configuration registers;
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"config": PCIe configuration space registers.
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- msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
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- port-id: Should be 0, 1, 2 or 3.
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Optional properties:
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- status: Either "ok" or "disabled".
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- dma-coherent: Present if DMA operations are coherent.
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Hip05 Example (note that Hip06 is the same except compatible):
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pcie@b0080000 {
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compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
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reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>;
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reg-names = "rc_dbi", "config";
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bus-range = <0 15>;
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msi-parent = <&its_pcie>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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dma-coherent;
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ranges = <0x82000000 0 0x00000000 0x220 0x00000000 0 0x10000000>;
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num-lanes = <8>;
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port-id = <1>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <0x0 0 0 1 &mbigen_pcie 1 10
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0x0 0 0 2 &mbigen_pcie 2 11
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0x0 0 0 3 &mbigen_pcie 3 12
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0x0 0 0 4 &mbigen_pcie 4 13>;
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};
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