
Cadence driver uses "mem" memory resource to obtain the offset of configuration space address region, memory space address region and message space address region. The obtained offset is used to program the Address Translation Unit (ATU). However certain platforms like TI's J721E SoC require the absolute address to be programmed in the ATU and not just the offset. Add new *ops* for CPU addr fixup for the platform drivers to provide the correct address to be programmed in the ATU. Link: https://lore.kernel.org/r/20200722110317.4744-9-kishon@ti.com Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
188 lines
4.3 KiB
C
188 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Cadence PCIe platform driver.
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*
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* Copyright (c) 2019, Cadence Design Systems
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* Author: Tom Joseph <tjoseph@cadence.com>
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*/
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#include <linux/kernel.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/of_device.h>
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#include "pcie-cadence.h"
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#define CDNS_PLAT_CPU_TO_BUS_ADDR 0x0FFFFFFF
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/**
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* struct cdns_plat_pcie - private data for this PCIe platform driver
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* @pcie: Cadence PCIe controller
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* @is_rc: Set to 1 indicates the PCIe controller mode is Root Complex,
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* if 0 it is in Endpoint mode.
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*/
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struct cdns_plat_pcie {
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struct cdns_pcie *pcie;
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bool is_rc;
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};
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struct cdns_plat_pcie_of_data {
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bool is_rc;
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};
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static const struct of_device_id cdns_plat_pcie_of_match[];
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static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr)
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{
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return cpu_addr & CDNS_PLAT_CPU_TO_BUS_ADDR;
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}
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static const struct cdns_pcie_ops cdns_plat_ops = {
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.cpu_addr_fixup = cdns_plat_cpu_addr_fixup,
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};
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static int cdns_plat_pcie_probe(struct platform_device *pdev)
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{
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const struct cdns_plat_pcie_of_data *data;
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struct cdns_plat_pcie *cdns_plat_pcie;
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const struct of_device_id *match;
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struct device *dev = &pdev->dev;
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struct pci_host_bridge *bridge;
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struct cdns_pcie_ep *ep;
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struct cdns_pcie_rc *rc;
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int phy_count;
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bool is_rc;
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int ret;
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match = of_match_device(cdns_plat_pcie_of_match, dev);
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if (!match)
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return -EINVAL;
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data = (struct cdns_plat_pcie_of_data *)match->data;
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is_rc = data->is_rc;
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pr_debug(" Started %s with is_rc: %d\n", __func__, is_rc);
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cdns_plat_pcie = devm_kzalloc(dev, sizeof(*cdns_plat_pcie), GFP_KERNEL);
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if (!cdns_plat_pcie)
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return -ENOMEM;
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platform_set_drvdata(pdev, cdns_plat_pcie);
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if (is_rc) {
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if (!IS_ENABLED(CONFIG_PCIE_CADENCE_PLAT_HOST))
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return -ENODEV;
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bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
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if (!bridge)
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return -ENOMEM;
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rc = pci_host_bridge_priv(bridge);
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rc->pcie.dev = dev;
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rc->pcie.ops = &cdns_plat_ops;
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cdns_plat_pcie->pcie = &rc->pcie;
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cdns_plat_pcie->is_rc = is_rc;
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ret = cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie);
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if (ret) {
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dev_err(dev, "failed to init phy\n");
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return ret;
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}
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pm_runtime_enable(dev);
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ret = pm_runtime_get_sync(dev);
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if (ret < 0) {
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dev_err(dev, "pm_runtime_get_sync() failed\n");
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goto err_get_sync;
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}
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ret = cdns_pcie_host_setup(rc);
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if (ret)
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goto err_init;
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} else {
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if (!IS_ENABLED(CONFIG_PCIE_CADENCE_PLAT_EP))
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return -ENODEV;
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ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
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if (!ep)
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return -ENOMEM;
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ep->pcie.dev = dev;
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ep->pcie.ops = &cdns_plat_ops;
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cdns_plat_pcie->pcie = &ep->pcie;
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cdns_plat_pcie->is_rc = is_rc;
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ret = cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie);
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if (ret) {
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dev_err(dev, "failed to init phy\n");
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return ret;
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}
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pm_runtime_enable(dev);
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ret = pm_runtime_get_sync(dev);
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if (ret < 0) {
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dev_err(dev, "pm_runtime_get_sync() failed\n");
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goto err_get_sync;
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}
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ret = cdns_pcie_ep_setup(ep);
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if (ret)
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goto err_init;
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}
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err_init:
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pm_runtime_put_sync(dev);
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err_get_sync:
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pm_runtime_disable(dev);
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cdns_pcie_disable_phy(cdns_plat_pcie->pcie);
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phy_count = cdns_plat_pcie->pcie->phy_count;
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while (phy_count--)
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device_link_del(cdns_plat_pcie->pcie->link[phy_count]);
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return 0;
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}
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static void cdns_plat_pcie_shutdown(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct cdns_pcie *pcie = dev_get_drvdata(dev);
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int ret;
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ret = pm_runtime_put_sync(dev);
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if (ret < 0)
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dev_dbg(dev, "pm_runtime_put_sync failed\n");
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pm_runtime_disable(dev);
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cdns_pcie_disable_phy(pcie);
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}
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static const struct cdns_plat_pcie_of_data cdns_plat_pcie_host_of_data = {
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.is_rc = true,
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};
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static const struct cdns_plat_pcie_of_data cdns_plat_pcie_ep_of_data = {
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.is_rc = false,
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};
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static const struct of_device_id cdns_plat_pcie_of_match[] = {
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{
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.compatible = "cdns,cdns-pcie-host",
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.data = &cdns_plat_pcie_host_of_data,
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},
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{
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.compatible = "cdns,cdns-pcie-ep",
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.data = &cdns_plat_pcie_ep_of_data,
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},
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{},
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};
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static struct platform_driver cdns_plat_pcie_driver = {
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.driver = {
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.name = "cdns-pcie",
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.of_match_table = cdns_plat_pcie_of_match,
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.pm = &cdns_pcie_pm_ops,
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},
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.probe = cdns_plat_pcie_probe,
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.shutdown = cdns_plat_pcie_shutdown,
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};
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builtin_platform_driver(cdns_plat_pcie_driver);
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