cfd54de3b0
MIPS_ISA_LEVEL is always defined as the 64 bit ISA that is a compatible superset of the ISA that the kernel build is targeting, and is used to allow us to emit instructions that we may detect support for at runtime. When we use a .set MIPS_ISA_LEVEL directive & are building a 32-bit kernel, we therefore are temporarily allowing the assembler to generate MIPS64 instructions. Using the move pseudo-instruction whilst this is the case is problematic because the assembler is likely to emit a daddu instruction which will generate a reserved instruction exception when executed on a MIPS32 machine. Unfortunately the combination of commita0a5ac3ce8("MIPS: Fix delay slot bug in `atomic*_sub_if_positive' for R10000_LLSC_WAR") and commit4936084c2e("MIPS: Cleanup R10000_LLSC_WAR logic in atomic.h") causes us to do exactly this in atomic_sub_if_positive(), and the result is MIPS64 daddu instructions in 32-bit kernels. Fix this by using .set mips0 to restore the default ISA after the ll instruction, and use .set MIPS_ISA_LEVEL again prior to the sc. This ensures everything but the ll & sc are assembled using the default ISA for the kernel build & the move pseudo-instruction is emitted as a MIPS32 addu instruction. We appear to have another pre-existing instance of the same issue in our atomic_fetch_*_relaxed() functions, and fix that up too by moving our .set move0 such that it occurs prior to use of the move pseudo-instruction. Signed-off-by: Paul Burton <paul.burton@mips.com> Fixes:a0a5ac3ce8("MIPS: Fix delay slot bug in `atomic*_sub_if_positive' for R10000_LLSC_WAR") Fixes:4936084c2e("MIPS: Cleanup R10000_LLSC_WAR logic in atomic.h") Patchwork: https://patchwork.linux-mips.org/patch/20253/ Cc: James Hogan <jhogan@kernel.org> Cc: Joshua Kinard <kumba@gentoo.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org
598 lines
16 KiB
C
598 lines
16 KiB
C
/*
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* Atomic operations that C can't guarantee us. Useful for
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* resource counting etc..
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*
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* But use these as seldom as possible since they are much more slower
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* than regular operations.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 97, 99, 2000, 03, 04, 06 by Ralf Baechle
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*/
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#ifndef _ASM_ATOMIC_H
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#define _ASM_ATOMIC_H
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#include <linux/irqflags.h>
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#include <linux/types.h>
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#include <asm/barrier.h>
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#include <asm/compiler.h>
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#include <asm/cpu-features.h>
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#include <asm/cmpxchg.h>
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#include <asm/war.h>
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/*
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* Using a branch-likely instruction to check the result of an sc instruction
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* works around a bug present in R10000 CPUs prior to revision 3.0 that could
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* cause ll-sc sequences to execute non-atomically.
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*/
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#if R10000_LLSC_WAR
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# define __scbeqz "beqzl"
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#else
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# define __scbeqz "beqz"
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#endif
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#define ATOMIC_INIT(i) { (i) }
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/*
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* atomic_read - read atomic variable
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* @v: pointer of type atomic_t
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*
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* Atomically reads the value of @v.
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*/
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#define atomic_read(v) READ_ONCE((v)->counter)
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/*
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* atomic_set - set atomic variable
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* @v: pointer of type atomic_t
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* @i: required value
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*
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* Atomically sets the value of @v to @i.
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*/
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#define atomic_set(v, i) WRITE_ONCE((v)->counter, (i))
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#define ATOMIC_OP(op, c_op, asm_op) \
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static __inline__ void atomic_##op(int i, atomic_t * v) \
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{ \
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if (kernel_uses_llsc) { \
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int temp; \
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\
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__asm__ __volatile__( \
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" .set "MIPS_ISA_LEVEL" \n" \
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"1: ll %0, %1 # atomic_" #op " \n" \
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" " #asm_op " %0, %2 \n" \
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" sc %0, %1 \n" \
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"\t" __scbeqz " %0, 1b \n" \
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" .set mips0 \n" \
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} else { \
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unsigned long flags; \
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\
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raw_local_irq_save(flags); \
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v->counter c_op i; \
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raw_local_irq_restore(flags); \
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} \
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}
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#define ATOMIC_OP_RETURN(op, c_op, asm_op) \
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static __inline__ int atomic_##op##_return_relaxed(int i, atomic_t * v) \
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{ \
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int result; \
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\
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if (kernel_uses_llsc) { \
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int temp; \
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\
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__asm__ __volatile__( \
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" .set "MIPS_ISA_LEVEL" \n" \
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"1: ll %1, %2 # atomic_" #op "_return \n" \
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" " #asm_op " %0, %1, %3 \n" \
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" sc %0, %2 \n" \
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"\t" __scbeqz " %0, 1b \n" \
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" " #asm_op " %0, %1, %3 \n" \
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" .set mips0 \n" \
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: "=&r" (result), "=&r" (temp), \
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"+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} else { \
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unsigned long flags; \
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\
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raw_local_irq_save(flags); \
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result = v->counter; \
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result c_op i; \
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v->counter = result; \
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raw_local_irq_restore(flags); \
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} \
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\
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return result; \
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}
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#define ATOMIC_FETCH_OP(op, c_op, asm_op) \
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static __inline__ int atomic_fetch_##op##_relaxed(int i, atomic_t * v) \
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{ \
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int result; \
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\
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if (kernel_uses_llsc) { \
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int temp; \
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\
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__asm__ __volatile__( \
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" .set "MIPS_ISA_LEVEL" \n" \
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"1: ll %1, %2 # atomic_fetch_" #op " \n" \
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" " #asm_op " %0, %1, %3 \n" \
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" sc %0, %2 \n" \
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"\t" __scbeqz " %0, 1b \n" \
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" .set mips0 \n" \
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" move %0, %1 \n" \
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: "=&r" (result), "=&r" (temp), \
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"+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} else { \
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unsigned long flags; \
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\
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raw_local_irq_save(flags); \
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result = v->counter; \
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v->counter c_op i; \
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raw_local_irq_restore(flags); \
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} \
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\
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return result; \
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}
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#define ATOMIC_OPS(op, c_op, asm_op) \
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ATOMIC_OP(op, c_op, asm_op) \
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ATOMIC_OP_RETURN(op, c_op, asm_op) \
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ATOMIC_FETCH_OP(op, c_op, asm_op)
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ATOMIC_OPS(add, +=, addu)
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ATOMIC_OPS(sub, -=, subu)
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#define atomic_add_return_relaxed atomic_add_return_relaxed
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#define atomic_sub_return_relaxed atomic_sub_return_relaxed
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#define atomic_fetch_add_relaxed atomic_fetch_add_relaxed
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#define atomic_fetch_sub_relaxed atomic_fetch_sub_relaxed
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(op, c_op, asm_op) \
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ATOMIC_OP(op, c_op, asm_op) \
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ATOMIC_FETCH_OP(op, c_op, asm_op)
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ATOMIC_OPS(and, &=, and)
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ATOMIC_OPS(or, |=, or)
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ATOMIC_OPS(xor, ^=, xor)
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#define atomic_fetch_and_relaxed atomic_fetch_and_relaxed
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#define atomic_fetch_or_relaxed atomic_fetch_or_relaxed
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#define atomic_fetch_xor_relaxed atomic_fetch_xor_relaxed
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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/*
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* atomic_sub_if_positive - conditionally subtract integer from atomic variable
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* @i: integer value to subtract
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* @v: pointer of type atomic_t
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*
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* Atomically test @v and subtract @i if @v is greater or equal than @i.
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* The function returns the old value of @v minus @i.
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*/
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static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
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{
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int result;
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smp_mb__before_llsc();
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if (kernel_uses_llsc) {
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int temp;
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__asm__ __volatile__(
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" .set "MIPS_ISA_LEVEL" \n"
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"1: ll %1, %2 # atomic_sub_if_positive\n"
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" .set mips0 \n"
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" subu %0, %1, %3 \n"
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" move %1, %0 \n"
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" bltz %0, 1f \n"
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" .set "MIPS_ISA_LEVEL" \n"
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" sc %1, %2 \n"
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"\t" __scbeqz " %1, 1b \n"
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"1: \n"
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" .set mips0 \n"
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: "=&r" (result), "=&r" (temp),
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"+" GCC_OFF_SMALL_ASM() (v->counter)
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: "Ir" (i));
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} else {
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unsigned long flags;
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raw_local_irq_save(flags);
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result = v->counter;
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result -= i;
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if (result >= 0)
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v->counter = result;
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raw_local_irq_restore(flags);
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}
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smp_llsc_mb();
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return result;
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}
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#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
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#define atomic_xchg(v, new) (xchg(&((v)->counter), (new)))
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/**
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* __atomic_add_unless - add unless the number is a given value
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* @v: pointer of type atomic_t
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* @a: the amount to add to v...
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* @u: ...unless v is equal to u.
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*
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* Atomically adds @a to @v, so long as it was not @u.
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* Returns the old value of @v.
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*/
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static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
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{
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int c, old;
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c = atomic_read(v);
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for (;;) {
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if (unlikely(c == (u)))
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break;
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old = atomic_cmpxchg((v), c, c + (a));
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if (likely(old == c))
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break;
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c = old;
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}
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return c;
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}
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#define atomic_dec_return(v) atomic_sub_return(1, (v))
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#define atomic_inc_return(v) atomic_add_return(1, (v))
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/*
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* atomic_sub_and_test - subtract value from variable and test result
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* @i: integer value to subtract
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* @v: pointer of type atomic_t
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*
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* Atomically subtracts @i from @v and returns
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* true if the result is zero, or false for all
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* other cases.
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*/
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#define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0)
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/*
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* atomic_inc_and_test - increment and test
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1
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* and returns true if the result is zero, or false for all
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* other cases.
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*/
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#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
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/*
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* atomic_dec_and_test - decrement by 1 and test
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* @v: pointer of type atomic_t
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*
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* Atomically decrements @v by 1 and
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* returns true if the result is 0, or false for all other
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* cases.
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*/
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#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
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/*
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* atomic_dec_if_positive - decrement by 1 if old value positive
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* @v: pointer of type atomic_t
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*/
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#define atomic_dec_if_positive(v) atomic_sub_if_positive(1, v)
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/*
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* atomic_inc - increment atomic variable
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1.
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*/
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#define atomic_inc(v) atomic_add(1, (v))
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/*
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* atomic_dec - decrement and test
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* @v: pointer of type atomic_t
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*
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* Atomically decrements @v by 1.
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*/
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#define atomic_dec(v) atomic_sub(1, (v))
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/*
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* atomic_add_negative - add and test if negative
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* @v: pointer of type atomic_t
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* @i: integer value to add
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*
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* Atomically adds @i to @v and returns true
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* if the result is negative, or false when
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* result is greater than or equal to zero.
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*/
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#define atomic_add_negative(i, v) (atomic_add_return(i, (v)) < 0)
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#ifdef CONFIG_64BIT
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#define ATOMIC64_INIT(i) { (i) }
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/*
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* atomic64_read - read atomic variable
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* @v: pointer of type atomic64_t
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*
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*/
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#define atomic64_read(v) READ_ONCE((v)->counter)
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/*
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* atomic64_set - set atomic variable
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* @v: pointer of type atomic64_t
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* @i: required value
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*/
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#define atomic64_set(v, i) WRITE_ONCE((v)->counter, (i))
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#define ATOMIC64_OP(op, c_op, asm_op) \
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static __inline__ void atomic64_##op(long i, atomic64_t * v) \
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{ \
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if (kernel_uses_llsc) { \
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long temp; \
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\
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__asm__ __volatile__( \
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" .set "MIPS_ISA_LEVEL" \n" \
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"1: lld %0, %1 # atomic64_" #op " \n" \
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" " #asm_op " %0, %2 \n" \
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" scd %0, %1 \n" \
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"\t" __scbeqz " %0, 1b \n" \
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" .set mips0 \n" \
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: "=&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} else { \
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unsigned long flags; \
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\
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raw_local_irq_save(flags); \
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v->counter c_op i; \
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raw_local_irq_restore(flags); \
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} \
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}
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#define ATOMIC64_OP_RETURN(op, c_op, asm_op) \
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static __inline__ long atomic64_##op##_return_relaxed(long i, atomic64_t * v) \
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{ \
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long result; \
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\
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if (kernel_uses_llsc) { \
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long temp; \
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\
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__asm__ __volatile__( \
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" .set "MIPS_ISA_LEVEL" \n" \
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"1: lld %1, %2 # atomic64_" #op "_return\n" \
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" " #asm_op " %0, %1, %3 \n" \
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" scd %0, %2 \n" \
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"\t" __scbeqz " %0, 1b \n" \
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" " #asm_op " %0, %1, %3 \n" \
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" .set mips0 \n" \
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: "=&r" (result), "=&r" (temp), \
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"+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} else { \
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unsigned long flags; \
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\
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raw_local_irq_save(flags); \
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result = v->counter; \
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result c_op i; \
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v->counter = result; \
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raw_local_irq_restore(flags); \
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} \
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\
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return result; \
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}
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#define ATOMIC64_FETCH_OP(op, c_op, asm_op) \
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static __inline__ long atomic64_fetch_##op##_relaxed(long i, atomic64_t * v) \
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{ \
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long result; \
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\
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if (kernel_uses_llsc && R10000_LLSC_WAR) { \
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long temp; \
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\
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__asm__ __volatile__( \
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" .set "MIPS_ISA_LEVEL" \n" \
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"1: lld %1, %2 # atomic64_fetch_" #op "\n" \
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" " #asm_op " %0, %1, %3 \n" \
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" scd %0, %2 \n" \
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"\t" __scbeqz " %0, 1b \n" \
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" move %0, %1 \n" \
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" .set mips0 \n" \
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: "=&r" (result), "=&r" (temp), \
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"+" GCC_OFF_SMALL_ASM() (v->counter) \
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: "Ir" (i)); \
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} else { \
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unsigned long flags; \
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\
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raw_local_irq_save(flags); \
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result = v->counter; \
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v->counter c_op i; \
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raw_local_irq_restore(flags); \
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} \
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\
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return result; \
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}
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#define ATOMIC64_OPS(op, c_op, asm_op) \
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ATOMIC64_OP(op, c_op, asm_op) \
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ATOMIC64_OP_RETURN(op, c_op, asm_op) \
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ATOMIC64_FETCH_OP(op, c_op, asm_op)
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ATOMIC64_OPS(add, +=, daddu)
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ATOMIC64_OPS(sub, -=, dsubu)
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#define atomic64_add_return_relaxed atomic64_add_return_relaxed
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#define atomic64_sub_return_relaxed atomic64_sub_return_relaxed
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#define atomic64_fetch_add_relaxed atomic64_fetch_add_relaxed
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#define atomic64_fetch_sub_relaxed atomic64_fetch_sub_relaxed
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#undef ATOMIC64_OPS
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#define ATOMIC64_OPS(op, c_op, asm_op) \
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ATOMIC64_OP(op, c_op, asm_op) \
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ATOMIC64_FETCH_OP(op, c_op, asm_op)
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ATOMIC64_OPS(and, &=, and)
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ATOMIC64_OPS(or, |=, or)
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ATOMIC64_OPS(xor, ^=, xor)
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#define atomic64_fetch_and_relaxed atomic64_fetch_and_relaxed
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#define atomic64_fetch_or_relaxed atomic64_fetch_or_relaxed
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#define atomic64_fetch_xor_relaxed atomic64_fetch_xor_relaxed
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#undef ATOMIC64_OPS
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#undef ATOMIC64_FETCH_OP
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#undef ATOMIC64_OP_RETURN
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#undef ATOMIC64_OP
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/*
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* atomic64_sub_if_positive - conditionally subtract integer from atomic
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* variable
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* @i: integer value to subtract
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* @v: pointer of type atomic64_t
|
|
*
|
|
* Atomically test @v and subtract @i if @v is greater or equal than @i.
|
|
* The function returns the old value of @v minus @i.
|
|
*/
|
|
static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
|
|
{
|
|
long result;
|
|
|
|
smp_mb__before_llsc();
|
|
|
|
if (kernel_uses_llsc) {
|
|
long temp;
|
|
|
|
__asm__ __volatile__(
|
|
" .set "MIPS_ISA_LEVEL" \n"
|
|
"1: lld %1, %2 # atomic64_sub_if_positive\n"
|
|
" dsubu %0, %1, %3 \n"
|
|
" move %1, %0 \n"
|
|
" bltz %0, 1f \n"
|
|
" scd %1, %2 \n"
|
|
"\t" __scbeqz " %1, 1b \n"
|
|
"1: \n"
|
|
" .set mips0 \n"
|
|
: "=&r" (result), "=&r" (temp),
|
|
"+" GCC_OFF_SMALL_ASM() (v->counter)
|
|
: "Ir" (i));
|
|
} else {
|
|
unsigned long flags;
|
|
|
|
raw_local_irq_save(flags);
|
|
result = v->counter;
|
|
result -= i;
|
|
if (result >= 0)
|
|
v->counter = result;
|
|
raw_local_irq_restore(flags);
|
|
}
|
|
|
|
smp_llsc_mb();
|
|
|
|
return result;
|
|
}
|
|
|
|
#define atomic64_cmpxchg(v, o, n) \
|
|
((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
|
|
#define atomic64_xchg(v, new) (xchg(&((v)->counter), (new)))
|
|
|
|
/**
|
|
* atomic64_add_unless - add unless the number is a given value
|
|
* @v: pointer of type atomic64_t
|
|
* @a: the amount to add to v...
|
|
* @u: ...unless v is equal to u.
|
|
*
|
|
* Atomically adds @a to @v, so long as it was not @u.
|
|
* Returns true iff @v was not @u.
|
|
*/
|
|
static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
|
|
{
|
|
long c, old;
|
|
c = atomic64_read(v);
|
|
for (;;) {
|
|
if (unlikely(c == (u)))
|
|
break;
|
|
old = atomic64_cmpxchg((v), c, c + (a));
|
|
if (likely(old == c))
|
|
break;
|
|
c = old;
|
|
}
|
|
return c != (u);
|
|
}
|
|
|
|
#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
|
|
|
|
#define atomic64_dec_return(v) atomic64_sub_return(1, (v))
|
|
#define atomic64_inc_return(v) atomic64_add_return(1, (v))
|
|
|
|
/*
|
|
* atomic64_sub_and_test - subtract value from variable and test result
|
|
* @i: integer value to subtract
|
|
* @v: pointer of type atomic64_t
|
|
*
|
|
* Atomically subtracts @i from @v and returns
|
|
* true if the result is zero, or false for all
|
|
* other cases.
|
|
*/
|
|
#define atomic64_sub_and_test(i, v) (atomic64_sub_return((i), (v)) == 0)
|
|
|
|
/*
|
|
* atomic64_inc_and_test - increment and test
|
|
* @v: pointer of type atomic64_t
|
|
*
|
|
* Atomically increments @v by 1
|
|
* and returns true if the result is zero, or false for all
|
|
* other cases.
|
|
*/
|
|
#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
|
|
|
|
/*
|
|
* atomic64_dec_and_test - decrement by 1 and test
|
|
* @v: pointer of type atomic64_t
|
|
*
|
|
* Atomically decrements @v by 1 and
|
|
* returns true if the result is 0, or false for all other
|
|
* cases.
|
|
*/
|
|
#define atomic64_dec_and_test(v) (atomic64_sub_return(1, (v)) == 0)
|
|
|
|
/*
|
|
* atomic64_dec_if_positive - decrement by 1 if old value positive
|
|
* @v: pointer of type atomic64_t
|
|
*/
|
|
#define atomic64_dec_if_positive(v) atomic64_sub_if_positive(1, v)
|
|
|
|
/*
|
|
* atomic64_inc - increment atomic variable
|
|
* @v: pointer of type atomic64_t
|
|
*
|
|
* Atomically increments @v by 1.
|
|
*/
|
|
#define atomic64_inc(v) atomic64_add(1, (v))
|
|
|
|
/*
|
|
* atomic64_dec - decrement and test
|
|
* @v: pointer of type atomic64_t
|
|
*
|
|
* Atomically decrements @v by 1.
|
|
*/
|
|
#define atomic64_dec(v) atomic64_sub(1, (v))
|
|
|
|
/*
|
|
* atomic64_add_negative - add and test if negative
|
|
* @v: pointer of type atomic64_t
|
|
* @i: integer value to add
|
|
*
|
|
* Atomically adds @i to @v and returns true
|
|
* if the result is negative, or false when
|
|
* result is greater than or equal to zero.
|
|
*/
|
|
#define atomic64_add_negative(i, v) (atomic64_add_return(i, (v)) < 0)
|
|
|
|
#endif /* CONFIG_64BIT */
|
|
|
|
#endif /* _ASM_ATOMIC_H */
|