c986a3d520
Make all definitions of the ColdFire Interrupt Source registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
109 lines
2.5 KiB
C
109 lines
2.5 KiB
C
/***************************************************************************/
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/*
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* linux/arch/m68knommu/platform/5249/config.c
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*
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* Copyright (C) 2002, Greg Ungerer (gerg@snapgear.com)
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*/
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/***************************************************************************/
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <asm/machdep.h>
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#include <asm/coldfire.h>
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#include <asm/mcfsim.h>
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/***************************************************************************/
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#ifdef CONFIG_M5249C3
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static struct resource m5249_smc91x_resources[] = {
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{
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.start = 0xe0000300,
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.end = 0xe0000300 + 0x100,
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.flags = IORESOURCE_MEM,
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},
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{
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.start = MCFINTC2_GPIOIRQ6,
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.end = MCFINTC2_GPIOIRQ6,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device m5249_smc91x = {
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.name = "smc91x",
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.id = 0,
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.num_resources = ARRAY_SIZE(m5249_smc91x_resources),
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.resource = m5249_smc91x_resources,
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};
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#endif /* CONFIG_M5249C3 */
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static struct platform_device *m5249_devices[] __initdata = {
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#ifdef CONFIG_M5249C3
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&m5249_smc91x,
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#endif
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};
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/***************************************************************************/
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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static void __init m5249_qspi_init(void)
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{
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/* QSPI irq setup */
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writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
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MCFSIM_QSPIICR);
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mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
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}
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#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
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/***************************************************************************/
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#ifdef CONFIG_M5249C3
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static void __init m5249_smc91x_init(void)
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{
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u32 gpio;
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/* Set the GPIO line as interrupt source for smc91x device */
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gpio = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
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writel(gpio | 0x40, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
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gpio = readl(MCF_MBAR2 + MCFSIM2_INTLEVEL5);
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writel(gpio | 0x04000000, MCF_MBAR2 + MCFSIM2_INTLEVEL5);
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}
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#endif /* CONFIG_M5249C3 */
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/***************************************************************************/
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void __init config_BSP(char *commandp, int size)
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{
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mach_sched_init = hw_timer_init;
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#ifdef CONFIG_M5249C3
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m5249_smc91x_init();
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#endif
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#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
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m5249_qspi_init();
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#endif
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}
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/***************************************************************************/
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static int __init init_BSP(void)
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{
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platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices));
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return 0;
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}
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arch_initcall(init_BSP);
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/***************************************************************************/
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