
Rockchip SoCs use 2 different numbering schemes. Where the gpio- controllers just count 0-31 for their 32 gpios, the underlying iomux controller splits these into 4 separate entities A-D. Device-schematics always use these iomux-values to identify pins, so to make mapping schematics to devicetree easier Andy Yan introduced named constants for the pins but so far we only used them on new additions. Using a sed-script created by Emil Renner Berthing bulk-convert the remaining raw gpio numbers into their descriptive counterparts and also gets rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x mappings: /rockchip,pins *=/bcheck b # to end of script :append-next-line N :check /^[^;]*$/bappend-next-line s/<RK_GPIO\([0-9]\) /<\1 /g s/<\([^ ][^ ]* *\)0 /<\1RK_PA0 /g s/<\([^ ][^ ]* *\)1 /<\1RK_PA1 /g s/<\([^ ][^ ]* *\)2 /<\1RK_PA2 /g s/<\([^ ][^ ]* *\)3 /<\1RK_PA3 /g s/<\([^ ][^ ]* *\)4 /<\1RK_PA4 /g s/<\([^ ][^ ]* *\)5 /<\1RK_PA5 /g s/<\([^ ][^ ]* *\)6 /<\1RK_PA6 /g s/<\([^ ][^ ]* *\)7 /<\1RK_PA7 /g s/<\([^ ][^ ]* *\)8 /<\1RK_PB0 /g s/<\([^ ][^ ]* *\)9 /<\1RK_PB1 /g s/<\([^ ][^ ]* *\)10 /<\1RK_PB2 /g s/<\([^ ][^ ]* *\)11 /<\1RK_PB3 /g s/<\([^ ][^ ]* *\)12 /<\1RK_PB4 /g s/<\([^ ][^ ]* *\)13 /<\1RK_PB5 /g s/<\([^ ][^ ]* *\)14 /<\1RK_PB6 /g s/<\([^ ][^ ]* *\)15 /<\1RK_PB7 /g s/<\([^ ][^ ]* *\)16 /<\1RK_PC0 /g s/<\([^ ][^ ]* *\)17 /<\1RK_PC1 /g s/<\([^ ][^ ]* *\)18 /<\1RK_PC2 /g s/<\([^ ][^ ]* *\)19 /<\1RK_PC3 /g s/<\([^ ][^ ]* *\)20 /<\1RK_PC4 /g s/<\([^ ][^ ]* *\)21 /<\1RK_PC5 /g s/<\([^ ][^ ]* *\)22 /<\1RK_PC6 /g s/<\([^ ][^ ]* *\)23 /<\1RK_PC7 /g s/<\([^ ][^ ]* *\)24 /<\1RK_PD0 /g s/<\([^ ][^ ]* *\)25 /<\1RK_PD1 /g s/<\([^ ][^ ]* *\)26 /<\1RK_PD2 /g s/<\([^ ][^ ]* *\)27 /<\1RK_PD3 /g s/<\([^ ][^ ]* *\)28 /<\1RK_PD4 /g s/<\([^ ][^ ]* *\)29 /<\1RK_PD5 /g s/<\([^ ][^ ]* *\)30 /<\1RK_PD6 /g s/<\([^ ][^ ]* *\)31 /<\1RK_PD7 /g s/<\([^ ][^ ]* *[^ ][^ ]* *\)0 /<\1RK_FUNC_GPIO /g s/<\([^ ][^ ]* *[^ ][^ ]* *\)RK_FUNC_\([1-9]\) /<\1\2 /g Suggested-by: Emil Renner Berthing <esmil@mailme.dk> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Katsuhiro Suzuki <katsuhiro@katsuster.net> Acked-by: Robin Murphy <robin.murphy@arm.com>
164 lines
3.0 KiB
Plaintext
164 lines
3.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Collabora Ltd.
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* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd.
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*
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* Schematics available at https://dl.vamrs.com/products/ficus/docs/hw
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*/
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/dts-v1/;
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#include "rk3399-rock960.dtsi"
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/ {
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model = "96boards RK3399 Ficus";
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compatible = "vamrs,ficus", "rockchip,rk3399";
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chosen {
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stdout-path = "serial2:1500000n8";
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};
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clkin_gmac: external-gmac-clock {
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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clock-output-names = "clkin_gmac";
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#clock-cells = <0>;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&user_led1>, <&user_led2>, <&user_led3>,
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<&user_led4>, <&wlan_led>, <&bt_led>;
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user_led1 {
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label = "red:user1";
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gpios = <&gpio4 25 0>;
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linux,default-trigger = "heartbeat";
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};
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user_led2 {
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label = "red:user2";
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gpios = <&gpio4 26 0>;
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linux,default-trigger = "mmc0";
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};
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user_led3 {
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label = "red:user3";
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gpios = <&gpio4 30 0>;
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linux,default-trigger = "mmc1";
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};
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user_led4 {
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label = "red:user4";
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gpios = <&gpio1 0 0>;
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panic-indicator;
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linux,default-trigger = "none";
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};
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wlan_active_led {
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label = "red:wlan";
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gpios = <&gpio1 1 0>;
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linux,default-trigger = "phy0tx";
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default-state = "off";
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};
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bt_active_led {
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label = "red:bt";
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gpios = <&gpio1 4 0>;
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linux,default-trigger = "hci0-power";
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default-state = "off";
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};
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};
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};
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&gmac {
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assigned-clocks = <&cru SCLK_RMII_SRC>;
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assigned-clock-parents = <&clkin_gmac>;
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clock_in_out = "input";
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phy-supply = <&vcc3v3_sys>;
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phy-mode = "rgmii";
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>;
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snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 10000 50000>;
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tx_delay = <0x28>;
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rx_delay = <0x11>;
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status = "okay";
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};
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&pcie0 {
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ep-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>;
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};
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&pinctrl {
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gmac {
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rgmii_sleep_pins: rgmii-sleep-pins {
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rockchip,pins =
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<3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>;
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};
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};
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pcie {
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pcie_drv: pcie-drv {
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rockchip,pins =
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<1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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usb2 {
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host_vbus_drv: host-vbus-drv {
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rockchip,pins =
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<4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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leds {
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user_led1: user_led1 {
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rockchip,pins =
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<4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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user_led2: user_led2 {
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rockchip,pins =
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<4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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user_led3: user_led3 {
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rockchip,pins =
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<4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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user_led4: user_led4 {
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rockchip,pins =
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<1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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wlan_led: wlan_led {
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rockchip,pins =
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<1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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bt_led: bt_led {
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rockchip,pins =
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<1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&usbdrd_dwc3_0 {
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dr_mode = "host";
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};
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&usbdrd_dwc3_1 {
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dr_mode = "host";
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};
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&vcc3v3_pcie {
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gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>;
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};
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&vcc5v0_host {
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gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
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};
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