8a2fe6c09f
Document the RZ/G1N (R8A7744) LVDS bindings. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Rob Herring <robh@kernel.org>
74 lines
2.6 KiB
Plaintext
74 lines
2.6 KiB
Plaintext
Renesas R-Car LVDS Encoder
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==========================
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These DT bindings describe the LVDS encoder embedded in the Renesas R-Car
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Gen2, R-Car Gen3 and RZ/G SoCs.
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Required properties:
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- compatible : Shall contain one of
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- "renesas,r8a7743-lvds" for R8A7743 (RZ/G1M) compatible LVDS encoders
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- "renesas,r8a7744-lvds" for R8A7744 (RZ/G1N) compatible LVDS encoders
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- "renesas,r8a774c0-lvds" for R8A774C0 (RZ/G2E) compatible LVDS encoders
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- "renesas,r8a7790-lvds" for R8A7790 (R-Car H2) compatible LVDS encoders
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- "renesas,r8a7791-lvds" for R8A7791 (R-Car M2-W) compatible LVDS encoders
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- "renesas,r8a7793-lvds" for R8A7793 (R-Car M2-N) compatible LVDS encoders
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- "renesas,r8a7795-lvds" for R8A7795 (R-Car H3) compatible LVDS encoders
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- "renesas,r8a7796-lvds" for R8A7796 (R-Car M3-W) compatible LVDS encoders
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- "renesas,r8a77965-lvds" for R8A77965 (R-Car M3-N) compatible LVDS encoders
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- "renesas,r8a77970-lvds" for R8A77970 (R-Car V3M) compatible LVDS encoders
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- "renesas,r8a77980-lvds" for R8A77980 (R-Car V3H) compatible LVDS encoders
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- "renesas,r8a77990-lvds" for R8A77990 (R-Car E3) compatible LVDS encoders
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- "renesas,r8a77995-lvds" for R8A77995 (R-Car D3) compatible LVDS encoders
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- reg: Base address and length for the memory-mapped registers
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- clocks: A list of phandles + clock-specifier pairs, one for each entry in
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the clock-names property.
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- clock-names: Name of the clocks. This property is model-dependent.
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- The functional clock, which mandatory for all models, shall be listed
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first, and shall be named "fck".
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- On R8A77990, R8A77995 and R8A774C0, the LVDS encoder can use the EXTAL or
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DU_DOTCLKINx clocks. Those clocks are optional. When supplied they must be
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named "extal" and "dclkin.x" respectively, with "x" being the DU_DOTCLKIN
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numerical index.
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- When the clocks property only contains the functional clock, the
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clock-names property may be omitted.
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- resets: A phandle + reset specifier for the module reset
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Required nodes:
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The LVDS encoder has two video ports. Their connections are modelled using the
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OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
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- Video port 0 corresponds to the parallel RGB input
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- Video port 1 corresponds to the LVDS output
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Each port shall have a single endpoint.
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Example:
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lvds0: lvds@feb90000 {
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compatible = "renesas,r8a7790-lvds";
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reg = <0 0xfeb90000 0 0x1c>;
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clocks = <&cpg CPG_MOD 726>;
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resets = <&cpg 726>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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lvds0_in: endpoint {
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remote-endpoint = <&du_out_lvds0>;
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};
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};
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port@1 {
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reg = <1>;
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lvds0_out: endpoint {
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};
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};
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};
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};
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