c7ed1ab3f7
This fixes up some of the I/D/F clock ambiguity in the sh-sci driver. The interface clock in most cases just wraps back to the peripheral clock, while the function clock wraps in to the MSTP bits. As the logic was somewhat inverted, this cleans that up, and also enables all CPUs with SCI MSTP bits to match function clocks through clkdev lookup. As a result, this gets rid of the clk string abuse on the sh side, and the clock string will be killed off once the ARM code has had a chance to sync up. This also enables MSTP gating on CPUs like 7786 which had never wired it up before. Impacted CPUs are primarily all SH-Mobiles, SH7785, and SH7786. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
461 lines
11 KiB
C
461 lines
11 KiB
C
/*
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* SH7366 Setup
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*
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* Copyright (C) 2008 Renesas Solutions
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*
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* Based on linux/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/serial_sci.h>
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#include <linux/uio_driver.h>
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#include <linux/sh_timer.h>
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#include <linux/usb/r8a66597.h>
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#include <asm/clock.h>
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static struct plat_sci_port scif0_platform_data = {
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.mapbase = 0xffe00000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 80, 80, 80, 80 },
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};
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static struct platform_device scif0_device = {
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.name = "sh-sci",
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.id = 0,
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.dev = {
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.platform_data = &scif0_platform_data,
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},
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};
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static struct resource iic_resources[] = {
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[0] = {
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.name = "IIC",
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.start = 0x04470000,
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.end = 0x04470017,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 96,
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.end = 99,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device iic_device = {
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.name = "i2c-sh_mobile",
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.id = 0, /* "i2c0" clock */
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.num_resources = ARRAY_SIZE(iic_resources),
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.resource = iic_resources,
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};
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static struct r8a66597_platdata r8a66597_data = {
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.on_chip = 1,
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};
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static struct resource usb_host_resources[] = {
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[0] = {
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.start = 0xa4d80000,
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.end = 0xa4d800ff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 65,
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.end = 65,
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.flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
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},
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};
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static struct platform_device usb_host_device = {
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.name = "r8a66597_hcd",
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.id = -1,
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.dev = {
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.dma_mask = NULL,
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.coherent_dma_mask = 0xffffffff,
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.platform_data = &r8a66597_data,
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},
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.num_resources = ARRAY_SIZE(usb_host_resources),
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.resource = usb_host_resources,
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};
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static struct uio_info vpu_platform_data = {
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.name = "VPU5",
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.version = "0",
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.irq = 60,
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};
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static struct resource vpu_resources[] = {
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[0] = {
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.name = "VPU",
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.start = 0xfe900000,
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.end = 0xfe902807,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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/* place holder for contiguous memory */
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},
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};
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static struct platform_device vpu_device = {
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.name = "uio_pdrv_genirq",
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.id = 0,
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.dev = {
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.platform_data = &vpu_platform_data,
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},
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.resource = vpu_resources,
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.num_resources = ARRAY_SIZE(vpu_resources),
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};
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static struct uio_info veu0_platform_data = {
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.name = "VEU",
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.version = "0",
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.irq = 54,
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};
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static struct resource veu0_resources[] = {
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[0] = {
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.name = "VEU(1)",
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.start = 0xfe920000,
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.end = 0xfe9200b7,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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/* place holder for contiguous memory */
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},
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};
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static struct platform_device veu0_device = {
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.name = "uio_pdrv_genirq",
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.id = 1,
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.dev = {
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.platform_data = &veu0_platform_data,
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},
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.resource = veu0_resources,
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.num_resources = ARRAY_SIZE(veu0_resources),
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};
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static struct uio_info veu1_platform_data = {
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.name = "VEU",
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.version = "0",
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.irq = 27,
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};
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static struct resource veu1_resources[] = {
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[0] = {
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.name = "VEU(2)",
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.start = 0xfe924000,
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.end = 0xfe9240b7,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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/* place holder for contiguous memory */
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},
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};
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static struct platform_device veu1_device = {
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.name = "uio_pdrv_genirq",
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.id = 2,
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.dev = {
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.platform_data = &veu1_platform_data,
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},
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.resource = veu1_resources,
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.num_resources = ARRAY_SIZE(veu1_resources),
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};
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static struct sh_timer_config cmt_platform_data = {
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.channel_offset = 0x60,
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.timer_bit = 5,
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.clk = "cmt0",
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.clockevent_rating = 125,
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.clocksource_rating = 200,
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};
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static struct resource cmt_resources[] = {
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[0] = {
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.start = 0x044a0060,
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.end = 0x044a006b,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 104,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device cmt_device = {
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.name = "sh_cmt",
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.id = 0,
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.dev = {
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.platform_data = &cmt_platform_data,
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},
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.resource = cmt_resources,
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.num_resources = ARRAY_SIZE(cmt_resources),
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};
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static struct sh_timer_config tmu0_platform_data = {
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.channel_offset = 0x04,
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.timer_bit = 0,
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.clk = "tmu0",
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.clockevent_rating = 200,
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};
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static struct resource tmu0_resources[] = {
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[0] = {
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.start = 0xffd80008,
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.end = 0xffd80013,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 16,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu0_device = {
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.name = "sh_tmu",
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.id = 0,
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.dev = {
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.platform_data = &tmu0_platform_data,
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},
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.resource = tmu0_resources,
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.num_resources = ARRAY_SIZE(tmu0_resources),
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};
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static struct sh_timer_config tmu1_platform_data = {
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.channel_offset = 0x10,
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.timer_bit = 1,
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.clk = "tmu0",
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.clocksource_rating = 200,
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};
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static struct resource tmu1_resources[] = {
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[0] = {
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.start = 0xffd80014,
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.end = 0xffd8001f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 17,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu1_device = {
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.name = "sh_tmu",
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.id = 1,
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.dev = {
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.platform_data = &tmu1_platform_data,
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},
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.resource = tmu1_resources,
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.num_resources = ARRAY_SIZE(tmu1_resources),
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};
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static struct sh_timer_config tmu2_platform_data = {
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.channel_offset = 0x1c,
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.timer_bit = 2,
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.clk = "tmu0",
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};
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static struct resource tmu2_resources[] = {
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[0] = {
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.start = 0xffd80020,
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.end = 0xffd8002b,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 18,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu2_device = {
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.name = "sh_tmu",
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.id = 2,
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.dev = {
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.platform_data = &tmu2_platform_data,
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},
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.resource = tmu2_resources,
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.num_resources = ARRAY_SIZE(tmu2_resources),
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};
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static struct platform_device *sh7366_devices[] __initdata = {
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&scif0_device,
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&cmt_device,
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&tmu0_device,
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&tmu1_device,
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&tmu2_device,
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&iic_device,
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&usb_host_device,
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&vpu_device,
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&veu0_device,
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&veu1_device,
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};
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static int __init sh7366_devices_setup(void)
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{
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platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
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platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
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platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
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return platform_add_devices(sh7366_devices,
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ARRAY_SIZE(sh7366_devices));
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}
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arch_initcall(sh7366_devices_setup);
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static struct platform_device *sh7366_early_devices[] __initdata = {
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&scif0_device,
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&cmt_device,
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&tmu0_device,
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&tmu1_device,
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&tmu2_device,
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};
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void __init plat_early_device_setup(void)
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{
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early_platform_add_devices(sh7366_early_devices,
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ARRAY_SIZE(sh7366_early_devices));
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}
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enum {
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UNUSED=0,
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/* interrupt sources */
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
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ICB,
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DMAC0, DMAC1, DMAC2, DMAC3,
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VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
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MFI, VPU, USB,
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MMC_MMC1I, MMC_MMC2I, MMC_MMC3I,
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DMAC4, DMAC5, DMAC_DADERR,
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SCIF, SCIFA1, SCIFA2,
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DENC, MSIOF,
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FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
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I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
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SDHI0, SDHI1, SDHI2, SDHI3,
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CMT, TSIF, SIU,
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TMU0, TMU1, TMU2,
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VEU2, LCDC,
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/* interrupt groups */
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DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C, SDHI,
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
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INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
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INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
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INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
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INTC_VECT(ICB, 0x700),
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INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
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INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
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INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
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INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
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INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), INTC_VECT(USB, 0xa20),
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INTC_VECT(MMC_MMC1I, 0xb00), INTC_VECT(MMC_MMC2I, 0xb20),
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INTC_VECT(MMC_MMC3I, 0xb40),
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INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
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INTC_VECT(DMAC_DADERR, 0xbc0),
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INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIFA1, 0xc20),
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INTC_VECT(SCIFA2, 0xc40),
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INTC_VECT(DENC, 0xc60), INTC_VECT(MSIOF, 0xc80),
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INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
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INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
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INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
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INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
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INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
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INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
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INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
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INTC_VECT(SIU, 0xf80),
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INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
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INTC_VECT(TMU2, 0x440),
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INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580),
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};
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
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INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
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INTC_GROUP(MMC, MMC_MMC1I, MMC_MMC2I, MMC_MMC3I),
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INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
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INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
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FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
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INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
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INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
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};
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static struct intc_mask_reg mask_registers[] __initdata = {
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{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
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{ } },
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{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
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{ VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
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{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
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{ 0, 0, 0, VPU, 0, 0, 0, MFI } },
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{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
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{ 0, 0, 0, ICB } },
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{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
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{ 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } },
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{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
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{ 0, DMAC_DADERR, DMAC5, DMAC4, DENC, SCIFA2, SCIFA1, SCIF } },
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{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
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{ 0, 0, 0, 0, 0, 0, 0, MSIOF } },
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{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
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{ I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
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FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
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{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
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{ SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, 0, SIU } },
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{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
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{ 0, 0, 0, CMT, 0, USB, } },
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{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
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{ 0, MMC_MMC3I, MMC_MMC2I, MMC_MMC1I } },
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{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
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{ 0, 0, 0, 0, 0, 0, 0, TSIF } },
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{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
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{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
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};
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
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{ 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } },
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{ 0xa4080008, 0, 16, 4, /* IPRC */ { } },
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{ 0xa408000c, 0, 16, 4, /* IPRD */ { } },
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{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
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{ 0xa4080014, 0, 16, 4, /* IPRF */ { 0, DMAC45, USB, CMT } },
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{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIFA1, SCIFA2, DENC } },
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{ 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF, 0, FLCTL, I2C } },
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{ 0xa4080020, 0, 16, 4, /* IPRI */ { 0, 0, TSIF, } },
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{ 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
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{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
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{ 0xa408002c, 0, 16, 4, /* IPRL */ { } },
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{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
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{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
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};
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|
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static struct intc_sense_reg sense_registers[] __initdata = {
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|
{ 0xa414001c, 16, 2, /* ICR1 */
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|
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
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|
};
|
|
|
|
static struct intc_mask_reg ack_registers[] __initdata = {
|
|
{ 0xa4140024, 0, 8, /* INTREQ00 */
|
|
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
|
|
};
|
|
|
|
static DECLARE_INTC_DESC_ACK(intc_desc, "sh7366", vectors, groups,
|
|
mask_registers, prio_registers, sense_registers,
|
|
ack_registers);
|
|
|
|
void __init plat_irq_setup(void)
|
|
{
|
|
register_intc_controller(&intc_desc);
|
|
}
|
|
|
|
void __init plat_mem_setup(void)
|
|
{
|
|
/* TODO: Register Node 1 */
|
|
}
|