d1fd4fb69e
This code changes the detection procedure of i7core_edac. Instead of directly probing for MC registers, it probes for another register found on Nehalem. If found, it tries to pick the first MC PCI BUS. This should work fine with Xeon 35xx, but, on Xeon 55xx, this is at bus 254 and 255 that are not properly detected by the non-legacy PCI methods. The new detection code scans specifically at buses 254 and 255 for the Xeon 55xx devices. This code has not tested yet. After working, a change at the code will be needed, since the i7core is not yet ready for working with 2 sets of MC. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
78 lines
1.6 KiB
C
78 lines
1.6 KiB
C
/*
|
|
* legacy.c - traditional, old school PCI bus probing
|
|
*/
|
|
#include <linux/init.h>
|
|
#include <linux/pci.h>
|
|
#include <asm/pci_x86.h>
|
|
|
|
/*
|
|
* Discover remaining PCI buses in case there are peer host bridges.
|
|
* We use the number of last PCI bus provided by the PCI BIOS.
|
|
*/
|
|
static void __devinit pcibios_fixup_peer_bridges(void)
|
|
{
|
|
int n;
|
|
|
|
if (pcibios_last_bus <= 0 || pcibios_last_bus > 0xff)
|
|
return;
|
|
DBG("PCI: Peer bridge fixup\n");
|
|
|
|
for (n=0; n <= pcibios_last_bus; n++)
|
|
pcibios_scan_specific_bus(n);
|
|
}
|
|
|
|
int __init pci_legacy_init(void)
|
|
{
|
|
if (!raw_pci_ops) {
|
|
printk("PCI: System does not support PCI\n");
|
|
return 0;
|
|
}
|
|
|
|
printk("PCI: Probing PCI hardware\n");
|
|
pci_root_bus = pcibios_scan_root(0);
|
|
if (pci_root_bus)
|
|
pci_bus_add_devices(pci_root_bus);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(pci_legacy_init);
|
|
|
|
void pcibios_scan_specific_bus(int busn)
|
|
{
|
|
int devfn;
|
|
long node;
|
|
u32 l;
|
|
|
|
if (pci_find_bus(0, busn))
|
|
return;
|
|
|
|
node = get_mp_bus_to_node(busn);
|
|
for (devfn = 0; devfn < 256; devfn += 8) {
|
|
if (!raw_pci_read(0, busn, devfn, PCI_VENDOR_ID, 2, &l) &&
|
|
l != 0x0000 && l != 0xffff) {
|
|
DBG("Found device at %02x:%02x [%04x]\n", busn, devfn, l);
|
|
printk(KERN_INFO "PCI: Discovered peer bus %02x\n", busn);
|
|
pci_scan_bus_on_node(busn, &pci_root_ops, node);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
EXPORT_SYMBOL_GPL(pcibios_scan_specific_bus);
|
|
|
|
int __init pci_subsys_init(void)
|
|
{
|
|
/*
|
|
* The init function returns an non zero value when
|
|
* pci_legacy_init should be invoked.
|
|
*/
|
|
if (x86_init.pci.init())
|
|
pci_legacy_init();
|
|
|
|
pcibios_fixup_peer_bridges();
|
|
x86_init.pci.init_irq();
|
|
pcibios_init();
|
|
|
|
return 0;
|
|
}
|
|
subsys_initcall(pci_subsys_init);
|