Dinh Nguyen 3b5015c4d8 clk: socfpga: stratix10: add additional clocks needed for the NAND IP ...

The nand_clk is actually called the nand_x_clk and the parent is the
l4_mp_clk, not the l4_main_clk. The nand_clk is a child of the
nand_x_clk and has a fixed divider of 4. The same is true for the
nand_ecc_clk.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

2019-06-25 14:36:56 -07:00

2.5 KiB

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