c1ca58f698
Currently, the NO_D3 flag is set in ish_probe(), and cleared in ish_remove(). So even if the system goes into S3, ISH is still in D0i3 state. It makes more sense that put ISH into D3 as system goes into S3 and put ISH into D0i3 as system goes into suspend-to-idle. I remove the NO_D3 setting in ish_probe(), so that ISH can enter D3 state when system enters S3. Only set N0_D3 flag when system enters the suspend-to-idle or platform specified, and clear it when system resume. When the ISH enters D3, the FW will check the DMA bit status. If the DMA bit is set, the FW will reset automatically. So the DMA bit need be clear before putting ISH into D3 state. Signed-off-by: Zhang Lixu <lixu.zhang@intel.com> Acked-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
83 lines
1.8 KiB
C
83 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* H/W layer of ISHTP provider device (ISH)
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*
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* Copyright (c) 2014-2016, Intel Corporation.
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*/
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#ifndef _ISHTP_HW_ISH_H_
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#define _ISHTP_HW_ISH_H_
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include "hw-ish-regs.h"
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#include "ishtp-dev.h"
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#define CHV_DEVICE_ID 0x22D8
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#define BXT_Ax_DEVICE_ID 0x0AA2
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#define BXT_Bx_DEVICE_ID 0x1AA2
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#define APL_Ax_DEVICE_ID 0x5AA2
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#define SPT_Ax_DEVICE_ID 0x9D35
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#define CNL_Ax_DEVICE_ID 0x9DFC
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#define GLK_Ax_DEVICE_ID 0x31A2
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#define CNL_H_DEVICE_ID 0xA37C
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#define ICL_MOBILE_DEVICE_ID 0x34FC
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#define SPT_H_DEVICE_ID 0xA135
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#define CML_LP_DEVICE_ID 0x02FC
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#define REVISION_ID_CHT_A0 0x6
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#define REVISION_ID_CHT_Ax_SI 0x0
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#define REVISION_ID_CHT_Bx_SI 0x10
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#define REVISION_ID_CHT_Kx_SI 0x20
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#define REVISION_ID_CHT_Dx_SI 0x30
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#define REVISION_ID_CHT_B0 0xB0
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#define REVISION_ID_SI_MASK 0x70
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struct ipc_rst_payload_type {
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uint16_t reset_id;
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uint16_t reserved;
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};
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struct time_sync_format {
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uint8_t ts1_source;
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uint8_t ts2_source;
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uint16_t reserved;
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} __packed;
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struct ipc_time_update_msg {
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uint64_t primary_host_time;
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struct time_sync_format sync_info;
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uint64_t secondary_host_time;
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} __packed;
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enum {
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HOST_UTC_TIME_USEC = 0,
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HOST_SYSTEM_TIME_USEC = 1
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};
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struct ish_hw {
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void __iomem *mem_addr;
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};
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/*
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* ISH FW status type
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*/
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enum {
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FWSTS_AFTER_RESET = 0,
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FWSTS_WAIT_FOR_HOST = 4,
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FWSTS_START_KERNEL_DMA = 5,
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FWSTS_FW_IS_RUNNING = 7,
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FWSTS_SENSOR_APP_LOADED = 8,
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FWSTS_SENSOR_APP_RUNNING = 15
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};
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#define to_ish_hw(dev) (struct ish_hw *)((dev)->hw)
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irqreturn_t ish_irq_handler(int irq, void *dev_id);
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struct ishtp_device *ish_dev_init(struct pci_dev *pdev);
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int ish_hw_start(struct ishtp_device *dev);
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void ish_device_disable(struct ishtp_device *dev);
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int ish_disable_dma(struct ishtp_device *dev);
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#endif /* _ISHTP_HW_ISH_H_ */
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