c11e3b48db
Probe the UARTs on SEAD3 boards using device tree rather than platform code, in order to reduce the amount of the latter. This requires that CONFIG_SERIAL_OF_PLATFORM be enabled, so enable it in sead3_defconfig. The SEAD3 DT shim code is extended to read bootloader environment variables to determine the appropriate UART & mode for kernel console output & set the stdout-path property of the chosen node accordingly. In contrast to the old platform code, which appears to have only ever set "console=ttyS0,38400n8r" with the code in console_config never having an effect, this will honor the "yamontty" environment variable to select between the 2 UARTs on the board and then check the "modetty0" or "modetty1" variable as appropriate to determine the UART configuration. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/14048/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
24 lines
643 B
C
24 lines
643 B
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved.
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* Douglas Leung <douglas@mips.com>
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* Steven J. Hill <sjhill@mips.com>
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*/
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#ifndef _MIPS_SEAD3INT_H
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#define _MIPS_SEAD3INT_H
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#include <linux/irqchip/mips-gic.h>
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/* CPU interrupt offsets */
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#define CPU_INT_EHCI 2
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#define CPU_INT_NET 6
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/* GIC interrupt offsets */
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#define GIC_INT_NET GIC_SHARED_TO_HWIRQ(0)
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#define GIC_INT_EHCI GIC_SHARED_TO_HWIRQ(5)
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#endif /* !(_MIPS_SEAD3INT_H) */
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