69501078fc
Add PCIe Host (RC) and Endpoint (EP) device tree schema for Cadence PCIe core library. Platforms using Cadence PCIe core can include the schemas added here in the platform specific schemas. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
32 lines
717 B
YAML
32 lines
717 B
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/pci/cdns-pcie.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Cadence PCIe Core
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maintainers:
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- Tom Joseph <tjoseph@cadence.com>
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properties:
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cdns,max-outbound-regions:
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description: maximum number of outbound regions
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 32
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default: 32
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phys:
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description:
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One per lane if more than one in the list. If only one PHY listed it must
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manage all lanes.
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minItems: 1
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maxItems: 16
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phy-names:
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items:
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- const: pcie-phy
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# FIXME: names when more than 1
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