192f0f8e9d
Pull powerpc updates from Michael Ellerman:
"Notable changes:
- Removal of the NPU DMA code, used by the out-of-tree Nvidia driver,
as well as some other functions only used by drivers that haven't
(yet?) made it upstream.
- A fix for a bug in our handling of hardware watchpoints (eg. perf
record -e mem: ...) which could lead to register corruption and
kernel crashes.
- Enable HAVE_ARCH_HUGE_VMAP, which allows us to use large pages for
vmalloc when using the Radix MMU.
- A large but incremental rewrite of our exception handling code to
use gas macros rather than multiple levels of nested CPP macros.
And the usual small fixes, cleanups and improvements.
Thanks to: Alastair D'Silva, Alexey Kardashevskiy, Andreas Schwab,
Aneesh Kumar K.V, Anju T Sudhakar, Anton Blanchard, Arnd Bergmann,
Athira Rajeev, Cédric Le Goater, Christian Lamparter, Christophe
Leroy, Christophe Lombard, Christoph Hellwig, Daniel Axtens, Denis
Efremov, Enrico Weigelt, Frederic Barrat, Gautham R. Shenoy, Geert
Uytterhoeven, Geliang Tang, Gen Zhang, Greg Kroah-Hartman, Greg Kurz,
Gustavo Romero, Krzysztof Kozlowski, Madhavan Srinivasan, Masahiro
Yamada, Mathieu Malaterre, Michael Neuling, Nathan Lynch, Naveen N.
Rao, Nicholas Piggin, Nishad Kamdar, Oliver O'Halloran, Qian Cai, Ravi
Bangoria, Sachin Sant, Sam Bobroff, Satheesh Rajendran, Segher
Boessenkool, Shaokun Zhang, Shawn Anastasio, Stewart Smith, Suraj
Jitindar Singh, Thiago Jung Bauermann, YueHaibing"
* tag 'powerpc-5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (163 commits)
powerpc/powernv/idle: Fix restore of SPRN_LDBAR for POWER9 stop state.
powerpc/eeh: Handle hugepages in ioremap space
ocxl: Update for AFU descriptor template version 1.1
powerpc/boot: pass CONFIG options in a simpler and more robust way
powerpc/boot: add {get, put}_unaligned_be32 to xz_config.h
powerpc/irq: Don't WARN continuously in arch_local_irq_restore()
powerpc/module64: Use symbolic instructions names.
powerpc/module32: Use symbolic instructions names.
powerpc: Move PPC_HA() PPC_HI() and PPC_LO() to ppc-opcode.h
powerpc/module64: Fix comment in R_PPC64_ENTRY handling
powerpc/boot: Add lzo support for uImage
powerpc/boot: Add lzma support for uImage
powerpc/boot: don't force gzipped uImage
powerpc/8xx: Add microcode patch to move SMC parameter RAM.
powerpc/8xx: Use IO accessors in microcode programming.
powerpc/8xx: replace #ifdefs by IS_ENABLED() in microcode.c
powerpc/8xx: refactor programming of microcode CPM params.
powerpc/8xx: refactor printing of microcode patch name.
powerpc/8xx: Refactor microcode write
powerpc/8xx: refactor writing of CPM microcode arrays
...
238 lines
3.7 KiB
ArmAsm
238 lines
3.7 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Floating-point, VMX/Altivec and VSX loads and stores
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* for use in instruction emulation.
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*
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* Copyright 2010 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
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*/
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#include <asm/processor.h>
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#include <asm/ppc_asm.h>
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#include <asm/ppc-opcode.h>
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#include <asm/reg.h>
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#include <asm/asm-offsets.h>
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#include <asm/asm-compat.h>
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#include <linux/errno.h>
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#define STKFRM (PPC_MIN_STKFRM + 16)
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/* Get the contents of frN into *p; N is in r3 and p is in r4. */
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_GLOBAL(get_fpr)
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mflr r0
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mfmsr r6
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ori r7, r6, MSR_FP
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MTMSRD(r7)
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isync
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rlwinm r3,r3,3,0xf8
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bcl 20,31,1f
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reg = 0
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.rept 32
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stfd reg, 0(r4)
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b 2f
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reg = reg + 1
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.endr
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1: mflr r5
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add r5,r3,r5
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mtctr r5
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mtlr r0
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bctr
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2: MTMSRD(r6)
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isync
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blr
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/* Put the contents of *p into frN; N is in r3 and p is in r4. */
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_GLOBAL(put_fpr)
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mflr r0
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mfmsr r6
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ori r7, r6, MSR_FP
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MTMSRD(r7)
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isync
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rlwinm r3,r3,3,0xf8
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bcl 20,31,1f
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reg = 0
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.rept 32
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lfd reg, 0(r4)
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b 2f
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reg = reg + 1
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.endr
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1: mflr r5
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add r5,r3,r5
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mtctr r5
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mtlr r0
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bctr
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2: MTMSRD(r6)
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isync
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blr
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#ifdef CONFIG_ALTIVEC
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/* Get the contents of vrN into *p; N is in r3 and p is in r4. */
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_GLOBAL(get_vr)
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mflr r0
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mfmsr r6
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oris r7, r6, MSR_VEC@h
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MTMSRD(r7)
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isync
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rlwinm r3,r3,3,0xf8
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bcl 20,31,1f
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reg = 0
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.rept 32
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stvx reg, 0, r4
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b 2f
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reg = reg + 1
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.endr
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1: mflr r5
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add r5,r3,r5
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mtctr r5
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mtlr r0
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bctr
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2: MTMSRD(r6)
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isync
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blr
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/* Put the contents of *p into vrN; N is in r3 and p is in r4. */
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_GLOBAL(put_vr)
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mflr r0
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mfmsr r6
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oris r7, r6, MSR_VEC@h
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MTMSRD(r7)
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isync
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rlwinm r3,r3,3,0xf8
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bcl 20,31,1f
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reg = 0
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.rept 32
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lvx reg, 0, r4
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b 2f
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reg = reg + 1
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.endr
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1: mflr r5
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add r5,r3,r5
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mtctr r5
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mtlr r0
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bctr
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2: MTMSRD(r6)
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isync
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blr
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#endif /* CONFIG_ALTIVEC */
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#ifdef CONFIG_VSX
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/* Get the contents of vsN into vs0; N is in r3. */
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_GLOBAL(get_vsr)
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mflr r0
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rlwinm r3,r3,3,0x1f8
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bcl 20,31,1f
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blr /* vs0 is already in vs0 */
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nop
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reg = 1
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.rept 63
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XXLOR(0,reg,reg)
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blr
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reg = reg + 1
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.endr
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1: mflr r5
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add r5,r3,r5
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mtctr r5
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mtlr r0
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bctr
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/* Put the contents of vs0 into vsN; N is in r3. */
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_GLOBAL(put_vsr)
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mflr r0
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rlwinm r3,r3,3,0x1f8
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bcl 20,31,1f
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blr /* v0 is already in v0 */
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nop
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reg = 1
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.rept 63
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XXLOR(reg,0,0)
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blr
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reg = reg + 1
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.endr
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1: mflr r5
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add r5,r3,r5
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mtctr r5
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mtlr r0
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bctr
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/* Load VSX reg N from vector doubleword *p. N is in r3, p in r4. */
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_GLOBAL(load_vsrn)
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PPC_STLU r1,-STKFRM(r1)
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mflr r0
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PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
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mfmsr r6
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oris r7,r6,MSR_VSX@h
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cmpwi cr7,r3,0
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li r8,STKFRM-16
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MTMSRD(r7)
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isync
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beq cr7,1f
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STXVD2X(0,R1,R8)
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1: LXVD2X(0,R0,R4)
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#ifdef __LITTLE_ENDIAN__
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XXSWAPD(0,0)
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#endif
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beq cr7,4f
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bl put_vsr
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LXVD2X(0,R1,R8)
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4: PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1)
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mtlr r0
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MTMSRD(r6)
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isync
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addi r1,r1,STKFRM
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blr
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/* Store VSX reg N to vector doubleword *p. N is in r3, p in r4. */
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_GLOBAL(store_vsrn)
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PPC_STLU r1,-STKFRM(r1)
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mflr r0
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PPC_STL r0,STKFRM+PPC_LR_STKOFF(r1)
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mfmsr r6
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oris r7,r6,MSR_VSX@h
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li r8,STKFRM-16
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MTMSRD(r7)
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isync
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STXVD2X(0,R1,R8)
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bl get_vsr
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#ifdef __LITTLE_ENDIAN__
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XXSWAPD(0,0)
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#endif
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STXVD2X(0,R0,R4)
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LXVD2X(0,R1,R8)
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PPC_LL r0,STKFRM+PPC_LR_STKOFF(r1)
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mtlr r0
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MTMSRD(r6)
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isync
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mr r3,r9
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addi r1,r1,STKFRM
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blr
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#endif /* CONFIG_VSX */
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/* Convert single-precision to double, without disturbing FPRs. */
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/* conv_sp_to_dp(float *sp, double *dp) */
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_GLOBAL(conv_sp_to_dp)
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mfmsr r6
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ori r7, r6, MSR_FP
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MTMSRD(r7)
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isync
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stfd fr0, -16(r1)
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lfs fr0, 0(r3)
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stfd fr0, 0(r4)
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lfd fr0, -16(r1)
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MTMSRD(r6)
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isync
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blr
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/* Convert single-precision to double, without disturbing FPRs. */
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/* conv_sp_to_dp(double *dp, float *sp) */
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_GLOBAL(conv_dp_to_sp)
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mfmsr r6
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ori r7, r6, MSR_FP
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MTMSRD(r7)
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isync
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stfd fr0, -16(r1)
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lfd fr0, 0(r3)
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stfs fr0, 0(r4)
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lfd fr0, -16(r1)
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MTMSRD(r6)
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isync
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blr
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